Martin Braun 13633dd543 fpga: Fix Xilinx bitfile parser for Python 3 ...

The script was previously only Python 2 compatible.

Python 2 support is now removed, so we don't maintain backwards
compatibility with Python 2.

This also fixes all linter warnings.


Original-commit: 6046e1a812ba2065d6ae13b4c4afdce8abc99d4f

2021-08-24 09:45:36 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

sim: Update chdr_16sc_to_sc12 testbench

2021-08-10 15:19:32 -05:00

sim

fpga: sim: Add PkgComplex, PkgMath, and PkgRandom

2021-08-08 14:59:26 -05:00

tools

fpga: Fix Xilinx bitfile parser for Python 3

2021-08-24 09:45:36 -05:00

top

N3xx: Fix White Rabbit

2021-08-04 15:19:58 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

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84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%