Lars Amsel 7ec0561c4d fpga: lib: Minor cleanup of axi_lite.vh ...

Original-commit: 2a5f0ea13e6d7d00798d6547e1170ff85d4aa42a

2021-06-03 09:34:20 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Minor cleanup of axi_lite.vh

2021-06-03 09:34:20 -05:00

sim

fpga: sim: Fix stream command and status models

2020-08-31 08:16:43 -05:00

tools

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00

top

fpga: e320: Improve timing on LVDS interface

2020-12-11 07:41:13 -06:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%