Commit Graph
161 Commits
Author SHA1 Message Date
Lars Amsel 7ec0561c4d fpga: lib: Minor cleanup of axi_lite.vh
Original-commit: 2a5f0ea13e6d7d00798d6547e1170ff85d4aa42a
2021-06-03 09:34:20 -05:00
Wade Fife 40c76b8d9a fpga: rfnoc: Add ability to disable output flow control
Per the RFNoC specification, if we set the frequency of flow
control updates to 0 then the input stream will not send flow control
status updates to the output stream handler.

This change makes it so that when the frequency of flow control status
updates is configured to be zero in the FPGA output stream handler
(i.e., cfg_fc_freq_bytes and cfg_fc_freq_pkts are both 0 in
chdr_stream_output) then the output stream handler will not use flow
control. That is, chdr_stream_output will not expect stream status
updates and will not restrict output packets.


Original-commit: 184999c54f0f30a7952d4e8560b393730c00e353
2021-04-14 07:24:49 -05:00
Wade Fife bababc79eb fpga: lib: Add rx_front_end_gen3 testbench
Original-commit: 532f8d0949c1d534b1a64600f2d32aadf2c7e202
2021-04-09 17:26:59 -05:00
Wade Fife 776860727e fpga: lib: Update round_sd to eliminate X from simulation
The asynchronous feedback loop on the err signal causes X to get stuck
on the sum signal when simulating. This change adds a check for
simulation only to force X to 0 so that unknown inputs get resolved
once the inputs are known.

Also added default values to the ports out and strobe_out, since having
them uninitialized and without reset was causing simulation issues in
other modules. The FPGA will initialize them to 0, so this change makes
the code equivalent to real hardware behavior.


Original-commit: b9f7af5807f73a5ac2612ea42ac2b65c26a3bff2
2021-04-09 17:26:59 -05:00
Wade Fife a300408721 fpga: lib: Fix simulation of axi_fir_filter
The always(*) block was never executing in some simulators because
there were no signals on the right-hand side in the block. Changing it
to an initial block ensures it always runs.


Original-commit: 0b965d579e2df962b91dac141eef6668f932e992
2021-04-09 17:26:59 -05:00
michael-west 4fa8a41e0b TwinRX: Remove frontend filter
Removing the FIR filter in the frontend to reclaim resources and remove
redundancy when using a DDC block.  The default image has a DDC block,
so only users making custom RFNoC images and using TwinRX will need to
take care to properly downconvert the full bandwidth coming from the
radio block.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: ad533eb6416c76d2a986c97fff846785ee56567e
2021-04-08 08:48:18 -05:00
Martin Braun dabe25774f fpga: docs: Improve documentation of rx_frontend_gen3
Also fixes a typo in the calibration manual page.


Original-commit: 3b3d3b6f9efb0fe685d9fabc8bdaca813549d9e3
2021-04-07 11:02:53 -05:00
Paul Butler c0b05cc4e4 fpga: lib: Fix DDS_SIN_COS_LUT outputs in makefile
Original-commit: 546ea894a0d5dd23dd046ef3b3c2d61acebefa98
2021-03-31 08:30:27 -05:00
Martin Braun 781636013c fpga: dsp: Fix formatting of rx_dcoffset and add docs
- Adapt to coding guide
- Add header that explains the module


Original-commit: 09995cc9954877cb56b4f028dc273f2d5fd0be10
2021-03-09 08:33:32 -06:00
Martin Braun ec4fab0340 fpga: Remove Python2 support from build system
- 2to3 was used to convert the Python scripts, except where the tool
  choked and manual intervention was required
- All references to "python" where replaced with "python3"
- buffer() was replaced by memoryview()


Original-commit: ca68195b5d12c5410cfac8d459a0b0902c4c72c7
2021-01-04 13:28:36 -06:00
Wade Fife ba66b26dc5 fpga: e320: Improve timing on LVDS interface
Original-commit: c6578eda2ba482b87583ebd989cdf5cbd5c3f672
2020-12-11 07:41:13 -06:00
Max Köhler 8eb950ac45 fpga: lib: add glitch free mux module
Original-commit: de3b48e89f2f9711b4b97c080d5c35baba45f573
2020-12-03 09:02:17 -06:00
Wade Fife e9a85d09ae fpga: e31x: Add OOT sources to Makefile.e31x.inc
Original-commit: e9454b48a19acc72870f61f1656cefd9e29c65ef
2020-11-13 14:01:13 -06:00
Wade Fife cc5c306897 fpga: lib: Fix axis_strm_monitor parameters
Original-commit: a51ccbba88d6a3f3012b84a1eed55725d41c7fd7
2020-10-20 21:10:16 -05:00
Andrew Moch e41c34776c fpga: lib: Fix small packets stuck in 10 GbE TX
Any packet less than CUT_THROUGH bytes has a high chance of getting
stuck in the TX FIFO of the xge_mac_wrapper. In cut-through mode we
were waiting for CUT_THROUGH bytes before transmitting the packet.


Original-commit: 1938bb951a981f4d3016b796f771b5047fb846a2
2020-10-05 16:03:21 -05:00
Andrew Moch 56d114b508 fpga: lib: Fix 10 GbE cut-through mode
When operating in cut-through mode the hold off from the MAC was not
applying back pressure, so when the TX interface filled up, data was
dropped. This bug was introduced when cut-through was added, and does
not impact the original implementation.


Original-commit: 6cd9662e2b8f2e159805015f3dd9087089a454af
2020-09-16 17:23:23 -05:00
Max Köhler 42d17bd090 fpga: lib: add generic to disable bitq engine tri-stating
Original-commit: b067b2af7924aa8577a8619f97d54122e0b71daf
2020-09-16 14:24:16 -05:00
Wade Fife f1d3374e50 fpga: e31x: Change image file to e310_rfnoc_image_core
This renames e31x_rfnoc_image_core.* to e310_rfnoc_image_core.*. This
makes the naming consistent with the rest of the build process (which
uses "e310" for all variants of e31x) and fixes an issue in which the
wrong file name was used by rfnoc_image_builder.


Original-commit: bbd43b16e18ef0a0311ddf4635cbd29c4ac3c367
2020-09-09 10:18:34 -07:00
michael-west bb7e7023e6 E320: Revert addition of Replay block
The DMA FIFO is needed for DDR3 BIST, so it is being restored for now.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 413ebee61254fd0b9ab0cd11b475b8a849579cd8
2020-09-04 15:45:51 -07:00
Aaron Rossetto 281efa74f1 fpga: Added AA image mappings to N320
Original-commit: 7e2fa6feb642b0970eafc68a0451ec4cde782106
2020-09-03 15:46:01 -05:00
mattprost 52172aaaf3 fpga: Add Replay Block to RFNoC Core Image
Add the Replay RFNoC block to the RFNoC core image for x300, x310, n300,
n310, n320/n321, and e320. The Replay block is contained within its own
static connection, so previous default behavior is still supported.

Signed-off-by: mattprost <matt.prost@ni.com>


Original-commit: 437381bd2cfe137c5e7e2a70aab8226bfb1c70cd
2020-09-03 15:26:33 -05:00
Wade Fife eab91d8ed0 fpga: Update DRAM IO signatures
This updates the IO signatures so that all devices and RFNoC blocks use
the same IO signature for the DRAM. This is needed because the IO
signatures must match between the RFNoC blocks and the devices. This
means that some devices have extra bits in the IO signature for the
address, but the extra bits will simply be ignored.


Original-commit: 8f09caaa06725d2364c63ac7cff02f3298895f4a
2020-09-03 15:26:33 -05:00
Wade Fife d6849765ec fpga: sim: chdr_stream_endpoint_tb improvements
- Adds test coverage for stream command and status packets
- Cleans up report output during simulation
- Stops clocks at the end of simulation, so chdr_stream_endpoint_tb can
  be run directly instead of just chdr_stream_endpoint_all_tb


Original-commit: 97cb396297828f57bba455a275966c58f1abce6e
2020-08-31 08:16:43 -05:00
Wade Fife 15d9d740ef fpga: sim: Fix stream command and status models
This updates PkgChdrBfm to correct some errors when modeling stream
command and stream status packets.

- Fix behavior when CHDR_W = 512
- Fix assertions in read_ctrl()


Original-commit: ccf5d1e0a06bf8d46d7bf6dc33a17e3228a1bff4
2020-08-31 08:16:43 -05:00
Wade Fife bd5d539bc2 fpga: n3xx: Update AXI interconnect address range
This change allows the entire 2 GiB address space to be accessed on
each memory port.


Original-commit: c6bb9924e56664ccb337694f8ef485ba8245edfd
2020-08-28 15:07:38 -05:00
Wade Fife 7e3f04d0ab fpga: e320: Update AXI interconnect address range
This change allows the entire 2 GiB address space to be accessed on
each memory port.


Original-commit: d352f5a9c3bd3791f0320be1e615146fe7459453
2020-08-28 15:07:38 -05:00
Wade Fife cf524e9af5 fpga: rfnoc: Update CHDR stream INIT command
This changes the behavior of the stream command with the INIT OpCode
such that sending the command with 0 for the values causes no flow
control stream status packets to be sent in response to incoming data.


Original-commit: 7c849afec4dad605ff6f32f7319933f99a4cd1ce
2020-08-28 15:02:41 -05:00
Wade Fife 0c6f2627a5 fpga: lib: Fix lint warnings
Fixes various synthesis/simulation warnings that were being generated
due to incorrectly sized constants.


Original-commit: 00f683c91486647f1711eb4c0b0a917078d29652
2020-08-28 15:02:41 -05:00
Wade Fife 09461da1f5 fpga: rfnoc: Remove deprecated files
Original-commit: db0d2dddcc5d8e39e2b7843a326ad9392bbb4c3f
2020-08-23 13:52:26 -05:00
Wade Fife 28955fb9f4 fpga: e31x: Change RFNoC Ctrl clock to 40 MHz
Original-commit: 8622a8013a429674de59cbff522b2722c8afa449
2020-08-19 12:28:22 -05:00
Wade Fife fd113147be fpga: e320: Fix timeout for timekeeper registers
This implements the same change that was made for E31x. The same issue
wasn't reproduced on N3xx, however this change keeps the code
consistent and eliminates the potential for the same problem.


Original-commit: 9c4a23f0a2a2d38ace75e4ab29f6f62f64155d81
2020-08-19 12:28:22 -05:00
Wade Fife 2253f7dbb0 fpga: n3xx: Fix timeout for timekeeper registers
This implements the same change that was made for E31x. The same issue
wasn't reproduced on N3xx, however this change keeps the code
consistent and eliminates the potential for the same problem.


Original-commit: e94a209c5b2559348593a6732d694fd49ab59ad0
2020-08-19 12:28:22 -05:00
Wade Fife f1380e5f33 fpga: e31x: Fix timeout for timekeeper registers
Fixing an issue in which a very slow radio_clk (due to low sample clock
rate) could cause bus transactions to be issued to the timekeeper
faster than it could service them, resulting in a timeout. This change
replaces RegPort with CtrlPort so that proper flow control can be
maintained to the timekeeper.


Original-commit: 2e910c5307702c3f3efb6dc8cb60f4f71ce11e67
2020-08-19 12:28:22 -05:00
Wade Fife 845dfd4f87 fpga: lib: Add more CtrlPort constants
Add some missing CtrlPort signal widths to ctrlport.vh.


Original-commit: c9d55d870dbccbc07ca9a7afaf2e0ac64944111c
2020-08-19 12:28:22 -05:00
Wade Fife 066948f87d fpga: lib: Add ctrlport_to_regport bridge
Original-commit: 5d9fb234d31fc5a13111c559a91a82e81c2487fc
2020-08-19 12:28:22 -05:00
Martin Braun 324f9d3c9a fpga: e320: Fix default YAML target to E320_1G
It was set to E320_HG, which is not a valid target, causing build errors
unless -t E320_1G was provided to rfnoc_image_builder.


Original-commit: 9ed42affcaa88e026cb4f82807e69b546ed30c8c
2020-08-17 07:56:30 -05:00
Wade Fife 20b814f62c fpga: e310: Fix device in image core YAML
Device was set to e31x, but this is not a valid device type. All e31x
devices use the e310 device type.


Original-commit: 60b76ebb31f9d1672c1b18367346b3fb522e13e9
2020-08-14 15:11:08 -05:00
Wade Fife b0c8336087 fpga: rfnoc: Enable clean switch in Switchboard
This change prevents packets from being chopped midway if the
switchboard configuration is changed when a packet is in flight.


Original-commit: f2ec5c91a79cee4c05465349d7e0da865ad1bead
2020-08-13 15:23:26 -05:00
Wade Fife 5a99bed5ee fpga: lib: Fix SWITCH_ON_LAST in axi_mux_select
Thange allows the mux to switch cleanly between packets, if the mux
select input is changed while a packet is in flight.


Original-commit: cee09d96aee51795ba2c6578f75f25f30ea11548
2020-08-13 15:23:26 -05:00
Max Köhler ec70691e84 fpga: lib: add handshake to replace FIFO for ctrlport CDC
The clock crossing of the ctrlport used FIFOs to transfer requests and responses
between clock domains. This commit adds a handshake based on the pulse
synchronizer to reduce the resource usage for ctrlport clock domain crossing.
Data is stored in a single register while the pulse synchronizer handles the
signaling of valid flags.


Original-commit: 2c2bb3a0b7269dcbd8b5933ce1c0c29ca17f599d
2020-08-13 07:46:14 -05:00
mattprost c91315d857 n320: Double radio ingress buffer size
This increases the size of the ingress buffers for the N320 radio to
support 250MHz TX streaming rates.

Signed-off-by: mattprost <matt.prost@ni.com>


Original-commit: e8db6fa4301ce471bf41ef14d5d38e5727199007
2020-08-12 15:17:48 -05:00
Wade Fife 8ed69c7cdb fpga: rfnoc: Fix clock crossing in axis_data_to_chdr
This fixes some incorrectly handled clock crossings from axis_data_clk
to axis_chdr_clk, which could have manifested as timing failures (on
E320) or incorrect behavior, depending on the product and noc_shell
configuration.

Also cleans up trailing white space.


Original-commit: f48af0a0876c99016eb8cd4558a31106bfc9baa1
2020-08-12 13:56:13 -05:00
Wade Fife 524ac02aaf fpga: lib: Change max FFT size to 1024
The max FFT size was 4096, but we don't currently have any devices that
can do that without modification. This is because, currently, the FFT
size must be the same as the packet size, and the largest packet
size supported by most devices is about 8000 bytes, or 2000
sc16 samples. Therefore, the largest FFT size supported without
modifying other code is 1024 samples.

This change frees up about 21% of the LUTs and 36% of the BRAM used by
axi_fft and makes the software block controller and the IP agree on the
maximum FFT size.


Original-commit: 4f387c8ff0571deedc86dc459e94e555b9768282
2020-08-11 16:20:51 -05:00
Wade Fife b4ea61f129 fpga: rfnoc: Add tests to FFT block
This adds additional tests to the testbench to cover register reads and
basic IFFT functionaltiy.


Original-commit: 9157e11795f3ca86dae2ee930e60a79470d1447f
2020-08-10 09:58:02 -05:00
Max Köhler 06afe79a42 fpga: lib: add Intel MAX10 architecture for 2clk FIFO
This commit derives parameters for MAX10 devices if provided by the
DEVICE parameter.

MAX10 devices FIFO generator support up to 36 bit wide FIFOs using
embedded memory (M9K) in simple dual port mode, which is treated
equally to RAM in the parameters.

In combination with sorting the ctrlport signals by usage, the used
resources can be reduced on the MAX10 devices from 6 to 3 M9K blocks
for a ctrlport_clk_cross instance without time and portids.


Original-commit: 0df2f9932cc270b8f1a705ea2543df8792005878
2020-08-06 16:17:33 -05:00
Andrew Moch f28357679e fpga: lib: Update xport_sv
- Detect dropped words at the dispatch level. This prevents
   an overflow on CHDR from block CPU.
 - Dropped packets are recorded as CPU or CHDR drop count
 - Refactor to put chdr_xport_adapter.sv in different clock
   domain to improve timing
 - Unwrinkle tkeep/trailing transitions


Original-commit: 7f86724ec3387f75d39d683b2ac5f5152e714c74
2020-08-05 17:18:12 -05:00
Aaron Rossetto 466e61d3ef fpga: rfnoc: Add RFNoC Keep One in N block
Original-commit: b39021ac2e642c22349183b6bc697daae01da5e9
2020-08-05 07:47:22 -05:00
Wade Fife 104a73e623 fpga: rfnoc: Add RFNoC Replay block
Original-commit: 6d92a1828121ca4b57d496bbf522820f961244b9
2020-08-04 15:40:08 -05:00
Wade Fife b4fed123c8 fpga: rfnoc: Add 4 KiB boundary check to sim_axi_ram
Adding a check for bursts that cross the 4 KiB boundary to the AXI4
memory model. Crossing a 4 KiB boundary is not allowed by AXI4.


Original-commit: 24f8bb39fd2769ff93d11b21152a834500152de4
2020-08-04 15:40:08 -05:00
Wade Fife 59f5dcfc4f fpga: rfnoc: Add support for CHDR_W < ITEM_W*NIPC
This change fixes the case where CHDR_W < ITEM_W*NIPC.

It also adds a state machine to stall the input to the pyld_fifo to
ensure that the pkt_info_fifo will not overflow. Previously in some
cases it allowed the same word to be inserted into the pyld_fifo
multiple times.


Original-commit: b862eda69cf41c7044a1805324f2fcfef5b0ba3d
2020-08-04 15:40:08 -05:00