Max Köhler 06afe79a42 fpga: lib: add Intel MAX10 architecture for 2clk FIFO ...

This commit derives parameters for MAX10 devices if provided by the
DEVICE parameter.

MAX10 devices FIFO generator support up to 36 bit wide FIFOs using
embedded memory (M9K) in simple dual port mode, which is treated
equally to RAM in the parameters.

In combination with sorting the ctrlport signals by usage, the used
resources can be reduced on the MAX10 devices from 6 to 3 M9K blocks
for a ctrlport_clk_cross instance without time and portids.


Original-commit: 0df2f9932cc270b8f1a705ea2543df8792005878

2020-08-06 16:17:33 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: add Intel MAX10 architecture for 2clk FIFO

2020-08-06 16:17:33 -05:00

sim

fpga: sim: Update PkgEthernet

2020-07-31 13:22:29 -05:00

tools

fpga: tools: RESOLVE_PATH checks for an empty path

2020-07-30 15:00:06 -05:00

top

fpga: n320: Add BIST (AA) image files

2020-07-31 14:32:54 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

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