miegl/b210-k7-fpga
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Andrew Moch f28357679e fpga: lib: Update xport_sv 
- Detect dropped words at the dispatch level. This prevents
   an overflow on CHDR from block CPU.
 - Dropped packets are recorded as CPU or CHDR drop count
 - Refactor to put chdr_xport_adapter.sv in different clock
   domain to improve timing
 - Unwrinkle tkeep/trailing transitions


Original-commit: 7f86724ec3387f75d39d683b2ac5f5152e714c74
2020-08-05 17:18:12 -05:00
export/x300/radio
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
lib
fpga: lib: Update xport_sv
2020-08-05 17:18:12 -05:00
sim
fpga: sim: Update PkgEthernet
2020-07-31 13:22:29 -05:00
tools
fpga: tools: RESOLVE_PATH checks for an empty path
2020-07-30 15:00:06 -05:00
top
fpga: n320: Add BIST (AA) image files
2020-07-31 14:32:54 -05:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
LICENSE.md
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
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