michael-west bb7e7023e6 E320: Revert addition of Replay block ...

The DMA FIFO is needed for DDR3 BIST, so it is being restored for now.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 413ebee61254fd0b9ab0cd11b475b8a849579cd8

2020-09-04 15:45:51 -07:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: sim: chdr_stream_endpoint_tb improvements

2020-08-31 08:16:43 -05:00

sim

fpga: sim: Fix stream command and status models

2020-08-31 08:16:43 -05:00

tools

fpga: Added AA image mappings to N320

2020-09-03 15:46:01 -05:00

top

E320: Revert addition of Replay block

2020-09-04 15:45:51 -07:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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