michael-west bb7e7023e6 E320: Revert addition of Replay block ...

The DMA FIFO is needed for DDR3 BIST, so it is being restored for now.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 413ebee61254fd0b9ab0cd11b475b8a849579cd8

2020-09-04 15:45:51 -07:00

..

b2xxmini

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

b200

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e31x

fpga: e31x: Change RFNoC Ctrl clock to 40 MHz

2020-08-19 12:28:22 -05:00

e320

E320: Revert addition of Replay block

2020-09-04 15:45:51 -07:00

n3xx

fpga: Add Replay Block to RFNoC Core Image

2020-09-03 15:26:33 -05:00

python

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

x300

fpga: Add Replay Block to RFNoC Core Image

2020-09-03 15:26:33 -05:00

Makefile.common

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00