Andrew Moch 8cb9bdd331 fpga: lib: Add AXI4 (full) interface ...

Add a SystemVerilog interface for connecting AXI4 ports, and an
associated header file with helper macros.


Original-commit: 04d29e85b0c0698e3de96b54fd3f6e04eb439f74

2021-06-03 11:26:54 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Add AXI4 (full) interface

2021-06-03 11:26:54 -05:00

sim

fpga: sim: Fix stream command and status models

2020-08-31 08:16:43 -05:00

tools

fpga: tools: Add ability to run commands before route

2021-06-03 10:22:04 -05:00

top

fpga: e320: Improve timing on LVDS interface

2020-12-11 07:41:13 -06:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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84 MiB

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