miegl/b210-k7-fpga
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Sam O'Brien 0bb7d1dd93 fpga: e31x: Upgrade to Vivado 2021.1 
Original-commit: 77f921c7c5d06095af5eb86a209348251edef07d
2022-08-25 13:55:30 -05:00
export/x300/radio
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
lib
fpga: lib: Upgrade to Vivado 2021.1
2022-08-25 13:55:30 -05:00
sim
fpga: Fix first arg in calls to $fatal()
2022-06-28 10:34:18 -05:00
tools
fpga: tools: Fix HLS IP builder for Vivado 2021.1
2022-08-25 13:55:30 -05:00
top
fpga: e31x: Upgrade to Vivado 2021.1
2022-08-25 13:55:30 -05:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
LICENSE.md
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
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84 MiB
Languages
Verilog 42.5%
VHDL 13%
SystemVerilog 12%
HTML 11.1%
C 9.6%
Other 11.6%