michael-west 8332f5b161 fpga: Fix sc16 to sc12 converter ...

Re-wrote converter to remove clock cycle delay on i_tready when handling
residual output and fixed improper handling of tlast during residual
data processing.  Resolves some USB overflow issues when using sc12 data
type on B200 devices.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 1fecf446e0358aa2b6a2d1f73a0daeac516435a0

2021-08-10 15:19:32 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: Fix sc16 to sc12 converter

2021-08-10 15:19:32 -05:00

sim

fpga: sim: Add PkgComplex, PkgMath, and PkgRandom

2021-08-08 14:59:26 -05:00

tools

fpga: sim: Add PkgComplex, PkgMath, and PkgRandom

2021-08-08 14:59:26 -05:00

top

N3xx: Fix White Rabbit

2021-08-04 15:19:58 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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