This adds the ability to do IP generation and FPGA builds using the
--jobs (-j) option with Make. For example, rather than generating each
IP one after another, you can generate up to N at a time using N Vivado
instances. This greatly reduces the IP generation time. Similarly,
parallel jobs can be used to easily build different FPGA variants
simultaneously.
Because FPGA builds can consume a lot of memory, care must be taken to
ensure that the number of jobs is not too high for the amount of memory
available.
New IP make targets were added for each USRP so that IP can be built
separately from the FPGA. The IP targets are now a dependency on each
FPGA target.
For example, you can generate the IP for X310 using 4 parallel jobs
using the following command:
make -j4 X310_IP
Or, build two X310 bitstreams simultaneously:
make -j2 X310_XG X310_HG
Original-commit: 4b03e237a96ee277eefff257d65b08708c38662c
The main changes included are:
- Variant-dependent pin-out instantiation.
- Update clocking scheme in top level file
to include XO3 PLL
- Add ability to shift outgoing data for
the GPIO communication interface with
the X410 FPGA.
- Include project files required to build
the XO3 variant of the ZBX CPLD.
- Add build flow for Lattice Diamond designs.
- Add ability to build XO3 variant of ZBX CPLD.
Original-commit: 2c7813acb21383f302353a1b6cf57f0946fa0b6b
This fixes warnings regarding the first argument to $fatal(), which is
supposed to be a number indicating what diagnostics to display. 1
corresponds to "Prints simulation time and location".
Original-commit: 58763bdfdaa276155ec6b79a3e5420de17172c7a
This causes the latest RFNoC protocol version to be used by default
and avoids the need to update YAML files every time the RFNoC
protocol version gets bumped.
Original-commit: 92016a585a5223a9a7678134e318e412875b64c2
- Added command time to readback of time from Radio block.
- Added wait for time to readback of shared registers in Radio block.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 8daa80c05f8006697aea05fea4ac5cd4dabbaef1
Extends timed command support to all endpoints
addressable by the radio ctrlport interface.
Previously supported endpoints:
- Daughterboard GPIO interface
- RFDC timing control
Newly supported endpoints:
- DIO ATR control
- DIO SPI control
- DIO Source control
Original-commit: e51f18925a566f152c4e8622aac6376efe46c6eb
- Add registers to read current record and play positions.
- Add register to read current space in play command FIFO to allow
software to avoid overflowing the FIFO.
- Cache base address and size with play command in command FIFO.
- Fix timestamp logic. Timestamp is only for the first packet of a
burst. The increment of 1 for each sample is not accurate because
it assumed the Replay block was playing at the same rate as the
Radio, which cannot be assumed.
Maintained backwards compatibility with older API.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 1545d3ff05f14b8dd175736b326fe6cae7dc830d
Update USRP RFNoC iamge core YAML files to use the more consistent
device port names. Clean up the formatting and make the files more
consistent.
Original-commit: 6318eaeff548f760056af7c8172937a296409d25
This updates all RFNoC devices so that they get the RFNoC protocol
version and CHDR width in the same way, from the output generated by
the RFNoC image builder.
Original-commit: 6f038dc2f69b38e715206b2e700fdd3a1bbc638e
Change name in DRAM IP Makefile from IP_MIG_7SERIES_TG_SRCS to
IP_DDR3_16BIT_TG_SRCS to match the naming of other variables.
Original-commit: febf339e0df412e54cf43a204c280128d8ca1ec3
Before this change, the packet size output by the Replay block during
playback was limited to length of a full memory burst transaction.
This led to relatively small packets during playback (typically
2 KiB) and had other side effects, such as simultaneous playback from
two different memory locations using different packet sizes because of
differences in memory alignment.
With this change, the configured packet size, as set by the register
REG_PLAY_WORDS_PER_PKT, is used for all packets except the last
packet of playback, which can of course be smaller.
Original-commit: 082a733c326d6332d581d5b7bf9ee86a503ba502
This sets the Replay block's counter width so that memory bursts are
up to 2 KiB. Previously, the counter width was fixed, which meant
that wide memories would require especially large buffers and could
exceed the 4 KiB limit imposed by AXI.
Original-commit: 08d03f881e2767f45ab7fc18c8003c9739b0ffb2
Change the width of the crossbar in the AXI Interconnect IP from
256-bit to 512-bit to match the DRAM memory controller width and to
give better performance.
Original-commit: 822cd03c8cd686f8b0554774adcbdd3803128bc2
Include a register that contains SPI controller information.
Currently, it only provides the number of slaves addressable
by the SPI engine.
Original-commit: 1d7d1226e7576bfad484109afd3aad4e78af111b
Modify behavior of clock crossing between radio_clk and radio_clk_2x.
This ensures strobe signals are always asserted for a single
radio_clk_2x cycle and when radio_clk is low.
Original-commit: adb352a2ad81d7c6d70ec5880a787b6bab7d19ba
The FSRU (aka EISCAT) was never supported in UHD 4.0. The FPGA
repository never had the relevant files, and the block controller also
never existed. This removes all the corresponding files from MPM, as
well as some references from makefiles.
Original-commit: ba00ff0cf5c0ced093e0be12b3006fe2f657a58a
This adds two additional ports to the DRAM, for a total of up to
four channels connected to DRAM.
Original-commit: a91d8e49655dd6f69ce1153498266c1a95230772
USRP N230 is no longer supported starting with UHD 4, and thus, we can
remove it from the image manifest. This will no longer download N230
images when calling uhd_images_downloader from UHD 4.
Original-commit: f1f6d8eac52bfecd840ace95c2d357641ae3b09c
Change AWIDTH to be the same as MEM_ADDR_W by default. Current USRPs
assume the AXI address width is the same as MEM_ADDR_W.
Original-commit: 6936a9ac664cbc312fd17a5ebab9b40069615f7a
This adds DRAM support to E31x devices. Due to the size of the DDR3
memory controller, it is not enabled by default. You can include the
memory controller IP in the build by adding the DRAM environment
variable to your build. For example:
DRAM=1 make E310_SG3
Original-commit: 788fef11ef890c6dcee3be495fc381bcf2990d3b
Sam O'Brien