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fpga: n3xx: Fix DRAM FIFO address alignment

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Original-commit: 59e35418ea5e6a0383e124425829e3de7dfa3237
This commit is contained in:
Wade Fife
2022-02-10 19:46:39 -07:00
parent 8589361e40
commit 1c0724aae2
3 changed files with 6 additions and 6 deletions
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top/n3xx/n300_bist_image_core.yml
+2 -2
View File
@@ -43,8 +43,8 @@ noc_blocks:
NUM_PORTS: 4
MEM_DATA_W: 64
MEM_ADDR_W: 31
FIFO_ADDR_BASE: "{30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}"
FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}"
FIFO_ADDR_BASE: "{31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}"
FIFO_ADDR_MASK: "{31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}"
MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz
# A list of all static connections in design
top/n3xx/n310_bist_image_core.yml
+2 -2
View File
@@ -51,8 +51,8 @@ noc_blocks:
NUM_PORTS: 4
MEM_DATA_W: 64
MEM_ADDR_W: 31
FIFO_ADDR_BASE: "{30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}"
FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}"
FIFO_ADDR_BASE: "{31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}"
FIFO_ADDR_MASK: "{31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}"
MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz
# A list of all static connections in design
top/n3xx/n320_bist_image_core.yml
+2 -2
View File
@@ -45,8 +45,8 @@ noc_blocks:
NUM_PORTS: 4
MEM_DATA_W: 64
MEM_ADDR_W: 31
FIFO_ADDR_BASE: "{30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}"
FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}"
FIFO_ADDR_BASE: "{31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}"
FIFO_ADDR_MASK: "{31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}"
MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz
# A list of all static connections in design