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fpga: rfnoc: Change AWIDTH default for axi_ram_fifo

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Change AWIDTH to be the same as MEM_ADDR_W by default. Current USRPs
assume the AXI address width is the same as MEM_ADDR_W.


Original-commit: 6936a9ac664cbc312fd17a5ebab9b40069615f7a
This commit is contained in:
Wade Fife
2022-02-10 19:46:39 -07:00
parent c322899053
commit 8589361e40
1 changed files with 1 additions and 1 deletions
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lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo.v
+1 -1
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@@ -66,7 +66,7 @@ module rfnoc_block_axi_ram_fifo #(
parameter MTU = 10,
parameter MEM_DATA_W = CHDR_W,
parameter MEM_ADDR_W = 32,
parameter AWIDTH = 32,
parameter AWIDTH = MEM_ADDR_W,
parameter [NUM_PORTS*MEM_ADDR_W-1:0] FIFO_ADDR_BASE = {NUM_PORTS{ {MEM_ADDR_W{1'b0}} }},
parameter [NUM_PORTS*MEM_ADDR_W-1:0] FIFO_ADDR_MASK = {NUM_PORTS{ {(MEM_ADDR_W-$clog2(NUM_PORTS)){1'b1}} }},
parameter [ NUM_PORTS*32-1:0] BURST_TIMEOUT = {NUM_PORTS{ 32'd256 }},