Wade Fife 8589361e40 fpga: rfnoc: Change AWIDTH default for axi_ram_fifo ...

Change AWIDTH to be the same as MEM_ADDR_W by default. Current USRPs
assume the AXI address width is the same as MEM_ADDR_W.


Original-commit: 6936a9ac664cbc312fd17a5ebab9b40069615f7a

2022-02-10 19:46:39 -07:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: rfnoc: Change AWIDTH default for axi_ram_fifo

2022-02-10 19:46:39 -07:00

sim

fpga: Remove noc_shell_regs.vh and sim_rfnoc_lib.svh

2022-01-25 14:09:15 -07:00

tools

images: Add utilization report files to B2xx image files

2022-02-10 11:35:47 -07:00

top

fpga: e31x: Add DRAM support

2022-02-10 18:13:44 -07:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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