Humberto Jimenez f53e3f27fc fpga: tools: Fix HLS IP builder for Vivado 2021.1 ...

Original-commit: 9300a0718274ede56cda3f48e43c9f0e1df4674b

2022-08-25 13:55:30 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: Update makefiles to allow parallel FPGA builds

2022-08-16 10:16:22 -05:00

sim

fpga: Fix first arg in calls to $fatal()

2022-06-28 10:34:18 -05:00

tools

fpga: tools: Fix HLS IP builder for Vivado 2021.1

2022-08-25 13:55:30 -05:00

top

fpga: Update makefiles to allow parallel FPGA builds

2022-08-16 10:16:22 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%