Sam O'Brien 959ce49389 fpga: tools: Allow IP renaming with viv_ip_xci_editor.py ...

Original-commit: e74f56b95a5ba8359468f2c4770e828731b8e1ef

2022-08-25 13:55:30 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: Update makefiles to allow parallel FPGA builds

2022-08-16 10:16:22 -05:00

sim

fpga: Fix first arg in calls to $fatal()

2022-06-28 10:34:18 -05:00

tools

fpga: tools: Allow IP renaming with viv_ip_xci_editor.py

2022-08-25 13:55:30 -05:00

top

fpga: Update makefiles to allow parallel FPGA builds

2022-08-16 10:16:22 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

No description provided

84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%