Javier Valenzuela 9513397e17 fpga: tools: Lattice build flow clean-up ...

Original-commit: fd2dd921a2af4bff1a26c43385b3942bc143f934

2022-08-03 14:28:21 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Update error call for undefined RW mode

2022-07-18 13:58:41 -06:00

sim

fpga: Fix first arg in calls to $fatal()

2022-06-28 10:34:18 -05:00

tools

fpga: tools: Lattice build flow clean-up

2022-08-03 14:28:21 -05:00

top

fpga: tools: Lattice build flow clean-up

2022-08-03 14:28:21 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

No description provided

84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%