Humberto Jimenez 44d37a616f fpga: lib: Add zynquplus family to axi_bitq ...

Original-commit: 87574a7c322f9f1af954bcee5dd9f59929992a85

2021-06-03 11:26:54 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Add zynquplus family to axi_bitq

2021-06-03 11:26:54 -05:00

sim

fpga: sim: Fix stream command and status models

2020-08-31 08:16:43 -05:00

tools

fpga: tools: Add ability to run commands before route

2021-06-03 10:22:04 -05:00

top

fpga: e320: Improve timing on LVDS interface

2020-12-11 07:41:13 -06:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

No description provided

84 MiB

0 Stars 1 Watchers 0 Forks

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%