Humberto Jimenez ad6b7bdee8 fpga: tools: Add support for RFSoC ...

This commit includes the following changes to the tools:
- Change part definition in XCI and BD editors for the RFSoC family
- Resolve part name in Vivado IP management utilities with
  viv_gen_part_id.py


Original-commit: fba23eb42c91ca1bc1108b5ba50c1b567cb9b59d

2021-06-03 10:22:04 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Minor cleanup of axi_lite.vh

2021-06-03 09:34:20 -05:00

sim

fpga: sim: Fix stream command and status models

2020-08-31 08:16:43 -05:00

tools

fpga: tools: Add support for RFSoC

2021-06-03 10:22:04 -05:00

top

fpga: e320: Improve timing on LVDS interface

2020-12-11 07:41:13 -06:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

No description provided

84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%