The module was failing with missing wire types when instantiated from
another module with a default wiretype of 'none'. To fix this, this
module was also moved to no default wire type.
Original-commit: 9d1e200d5e727b34339fc4ca9b6f94b28449747a
This updates the RFNoC image cores to separate the two DRAM banks on
X4xx by splitting them into "dram0" and "dram1". Previously, both DRAM
banks shared the same DRAM port, named "dram", which created some
confusion.
The Replay block has also been duplicated in the bitstreams that use
both banks, so we now have one Replay block per bank.
Original-commit: b5cfab8922e5b3f4ff13a8a64e8b0319876f13db
- Update X410 and X440 BSP YAML files to properly index clocks
- Update image core files to declare clock indices
- Update get_clocks() in MPM to return the correct values
This does not include changes to the x400_radio_control block registry.
This change by itself will thus not change behaviour.
Original-commit: f215af2ccde6420b685b4ca493c8bd71d28781cb
This adds support for the X440_X4_200 variant which supports up to
200 MHz bandwidth (250 Msps), has a DDC and DUC on each channel,
4 x 10 GbE interfaces, and no DRAM.
Original-commit: bdaba58750ce0c2ccc58769936c3c5c4a6b2d2cf
Adds a 266.667 MHz compute engine clock and uses it instead of the
radio clock for the DDC and DUC. Using a faster clock than the radio
allows the DDC and DUC to drain after a stall in the data flow.
Original-commit: ab93cb0929b9536b6d6cbfdc4813e6ba169053ae
Adds a 266.667 MHz compute engine clock and uses it instead of the
radio clock for the DDC and DUC. Using a faster clock than the radio
allows the DDC and DUC to drain after a stall in the data flow.
Original-commit: ff55d406a02cc934a5c238d22c836bea08ade3d1
Enable USE_AS_BUFF on packet gate to allow many packets to be buffered.
This reduces latency when several small packets are sent out close
together.
Original-commit: 32d348efe482d40c7090d8203a3c1374dfcb4a68
- Adds 6 bits each for an identifier for timebase and control clock
- Update all mako templates accordingly
Original-commit: 58c0276ff1ceaf825d7cbffbab5016ddef9a5cd9
Fix the TUSER width for some buses in eth_ipv4_chdr_adapter. This
allows wider CHDR widths to be used with 10 GbE.
Original-commit: f0ed58f7518410fc174a6356c072dfb21e3de253
FPGA:
- Split up MB registers that control daughterboard specific settings so
that daughterboards 0 and 1 could have different setings, in
preparation for future devices that require different settings.
This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
block/tile mapping of the individual channels, and information about
resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
them to their own headers, so it's trivial to add device-specific
sections of code instead for other devices in the future.
- This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
was unused and possibly broken.
- Move daughterboard-specific code into its own code location
(dboards/zbx)
- Move X410-specific register documentation to its own location
(doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
timekeeper)
MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
The frontend synchronization upon time change was removed, but is
required to synchronize the RX frontend modules when sharing LOs on
TwinRX. This change restores the behavior.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: c70b479007ab9f578577dfb5c2de6660e877d9a3
The time changed signal was removed and is needed to synchronized the
frontend. This restores the signal.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 27aad17956a063f72f192dde97cbff675b46fada
Gaps in transmission were seen when using the replay buffered TX
streamer caused by the Replay block setting the end of burst flag at the
end of every send() call. This fix adds a flag to the Replay block play
command register to avoid setting the end of burst flag and modifies the
replay buffered TX streamer to use the flag based on the metadata passed
in to the send() call.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 2419f405775934efa517e025929356ef0a0d181e
Module description:
Clock divider. Generates an output clock that is 1/N times the
frequency of the input clock.
Original-commit: 71bdcd22f07162687771d374178ad0372783bd45
Moves X4C_100, X4C_200, C1_100, and C1_200 from experimental to
available targets and makes the needed changes to allow them to build
successfully.
Adds support for "UC" FPGA variant. U indicates that QSFP0 is unused
and C indicates that QSFP1 is 100 GbE.
Adds experimental CG_200 variant.
Original-commit: cb9609c886b156e22ae9d879fffad8d060f2ca2d
Removes the CPU_W parameter from x4xx.v and the qsfp_wrapper files. The
value of this parameter depends on the axi_eth_dma IP and therefore
should not be changed.
Original-commit: 84c49f40adc980e2968a6a844b4bdbb2d2d38c9c
Martin Braun