- Removes target names for X3x0 and X4x0 builds (these are now encoded
in the YAML file)
- Change the image core YAML file names referenced in the pipeline YAMLs
to match the contents of fpga/usrp3/top/x?00/*.yml
- Remove X410_XG_100 image since it is not a shipping image
- Add image_core_name arguments for all E320, E31x, N3xx targets
Original-commit: 50e07a5b42d4a244c12b5a13b51048573d0069ec
- All RFNoC capable targets now require rfnoc_image_builder to be built
- `make help` is updated for all targets to provide more useful and
up-to-date information
- The FPGA manual is also updated
- All checked-in build artifacts are now removed from git
- axi_ram_fifo.yml is updated to provide include path information
(required for building N3xx BIST images, which use this)
Original-commit: 28b994406d4c9547b1e2add62781b6a8162fdb74
- Bumps FPGA compat from 8.2 to 8.3
- Adds three global motherboard registers to read the 96-bit device DNA
- MPM is updated to read these registers and update the device_info if
compat version 8.3 is available
Original-commit: ad5f97f8284057b85ca98f47365c2a321edf7ece
Most important effect of this change: rfnoc_image_builder is now
required to build bitfiles, 'make' alone won't suffice any longer!
This is a huge changeset to the image builder that combines multiple new
features:
- There no longer is a separate edge file for the static router. The
static routes are generated as a Verilog parameter directly into the
rfnoc_core_kernel (which is also modified).
- image_builder.py is split up into several smaller files. Code is moved
into yaml_utils.py, and the new files grc.py, builder_config.py
- Generic module support is added. Aside from noc blocks and stream
endpoints, we can now instantiate arbitrary modules (they also require
a YAML description file).
- To enable such modules, resets are now also tracked the same way that
clock domains are.
- The ImageBuilderConfig config object now more closes matches the
original YAML file. The attributes 'clk_domain_con' and 'block_con' are
removed. Instead, the attributes 'connections' and 'clk_domains' are
sanitized and amended with extra annotations. The templates are
updated to reflect this change.
- IO ports can now carry parameters, e.g., to have variable wire widths
based on the configuration.
- Many Pylint warnings were resolved.
- Add inheritance support for image core YAML files.
This allows image core files to (recursively) inherit from other image
core files. To do so, simply put an 'inherit' entry at the top of the
file:
```yaml
inherit: 'x410_radio_base.yml'
```
- The inheritance feature is used as part of the image core files.
- Image core and DTS files are now generated as a build artefact into
the build directory. This requires the usage of rfnoc_image_builder to
build images. As a consequence, it is no longer required to check in
image core Verilog files.
- As another consequence, rfnoc_image_builder is required to build
bitfiles!
- Image flavours are no longer defined through Makefiles, but purely
from the image core YAML files.
- Remove all image core YAML files that do not generate a shipping
image. Because of the inheritance feature and the requirement to use
the image builder, it is trivial to add new YAML files.
- Add support for transport adapters through the YAML files. Before,
transport adapters were inferred from the make target (e.g.,
X410_X4_200 would have four 10GbE links based on the 'X4' substring).
Now, transport adapters are defined via the image core YAML.
- This feature is currently only used (or can be used) by the X4xx
series. Older devices may or may not be ported to allow custom
transport adapters in the future.
- Add parameters to the BSP YAMLs and the devices itself. This allows
setting global parameters in the image core files. For example, the
X4x0 devices use this to decide if they instantiate DRAM channels.
- DTS includes and constraint files can now be requested by
blocks/transport adapter through their YAML files. They do no longer
need to be listed in the Makefile.
- Support for secure image cores. These are image cores that allow
incorporating RFNoC blocks that require license keys and thus can't
live in an open-source environment. This solution adds the option for
secure image cores without touching the open source feature set.
- Add --reuse option to allow manual editing of generated artefacts
- Allow IO signatures from any module: until now IO signatures had to be
defined in a single file (io_signatures). This file will persist. In
addition each module can add its own IO signature as with the same
format the core IO signatures placed under the top level key
`io_signatures`. IO signatures are still maintained in a global
dictionary. The consequence is that they can be shared among
independent modules as well as they have to have a globally unique
name. The image builder will warn about detected name clashes for the
signatures.
- As a consequence, some less commonly used IO signatures were moved to
their corresponding module YAML files.
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Lars Amsel <lars.amsel@ni.com>
Original-commit: a98ce2621e2a2dc25535fc700b49bfcb00b8eb59
The following modifications are applied to allow RFNoC blocks with zero
input- or output ports (or none at all):
- The backend interface will no longer synthesize any flushing logic if
there are no streaming ports
- The Mako templates are modified to allow generating code for blocks
without streaming ports
- The BFM for RFNoC blocks (RfnocBlockCtrlBfm) is partially factored out
into a parent class (RfnocBlockCtrlBfmCtrlOnly) which allows the
simulation of such RFNoC blocks
Original-commit: 878cfcf48f125826e9d48b7c61a4ee7fd19e9a94
- This provides a CtrlPort access to reading back the device DNA
- Available for US+ devices (i.e., RFSoC) and 7-series.
Original-commit: 43856f90da01cebc1e4b327f4435966ccd1df602
This modifies repeat_fpga_build.py such that it can take a YAML file as
input, not just a make target. It will then use the image builder to
prepare the build and generate a valid make command, which in turn is
used to build FPGA images repeatedly.
Original-commit: 09f3453f39363870f1c03ef1c917a0dedb7598df
This utility will regenerate all the image core .v files from the
available YAML files. It won't rebuild bitfiles.
Original-commit: 4861318d3bdccd8d1baa627a8473eb34f76583b1
This removes a duplicate code section that causes build warnings. It
also references a wire that gets declared further down and the removed
and remaining code sections were incorrectly indented.
Original-commit: e8084eb4cb4ec6ff6476feb6e77ab3ea45dd969e
In the build Makefiles, this adds a function (uniq) which removes
duplicate entries from lists. We apply this to the DESIGN_SRCS passed
to the Vivado build process. This eliminates some warnings from
duplicate source files caused by redundantly referencing source files in
the Makefiles, possibly because they are listed in more than one source
file variable.
Original-commit: 1944263412d329d53b32a17e9735b79e59e319d7
In several cases, we call `python` explicitly. On many modern operating
systems (e.g., Ubuntu 22.04), this command no longer exists, and if it
does, it's often an alias to python3.
Because the python3 executable has been around for so long, simply
using that directly (instead of, e.g., autodetecting the OS preferences)
is a simple fix that immediately allows building bitfiles, e.g. for the
B2xx series, on more recent OSes.
Original-commit: 356cd172bb5ae0d043825bd1f4dffbd6646ec3d2
The module was failing with missing wire types when instantiated from
another module with a default wiretype of 'none'. To fix this, this
module was also moved to no default wire type.
Original-commit: 9d1e200d5e727b34339fc4ca9b6f94b28449747a
- Update X410 and X440 BSP YAML files to properly index clocks
- Update image core files to declare clock indices
- Update get_clocks() in MPM to return the correct values
This does not include changes to the x400_radio_control block registry.
This change by itself will thus not change behaviour.
Original-commit: f215af2ccde6420b685b4ca493c8bd71d28781cb
- Adds 6 bits each for an identifier for timebase and control clock
- Update all mako templates accordingly
Original-commit: 58c0276ff1ceaf825d7cbffbab5016ddef9a5cd9
- Bump firmware compat to 6.1
- Remove crossbar counter logic (the FPGA does *not* support crossbar
counters anymore, so we remove it from the firmware as well)
- Remove crossbar programming control (this is now provided by RFNoC
management packets)
- Remove UDP framing control (this is also provided by RFNoC management
packets)
- Remove Ethernet link/activity LED control (this has been handled by
the FPGA directly for years now)
- Add functionality to program transport adapter. The TA is programmed
directly on the settings bus, so for the most part, this is already
possible from the firmware. The only exception is the 'virtual'
register to program IP address and MAC at the same time. In the
firmware, it will perform an ARP lookup of the MAC address, and then
write the "normal" IPv4 address register in the TA, as well as the MAC
address registers.
- Updated bootram.coe
Original-commit: 89fb75288e151cd1e43af765618c0665e79801f9
The 1/4-rate downconverter naively negated the input signals (y = -x)
which doesn't work when the signal is at full scale. In particular,
signals that are at full negative scale get converted to zeros (even
though 2's complement would be to return the same number, although that
would also be incorrect).
This fix changes it such that the smallest negative value gets converted
to the largest positive value.
This is not a mathematical correction inversion, but a minor amplitude
distortion. However, since we're already at full scale, and thus
probably clipping, this is preferable to the incorrect resolution of the
regular inversion. Put differently, there is no better value in this
case.
Original-commit: 8bd982745e6247cf3cf3da52925c65126287428a
The FSRU (aka EISCAT) was never supported in UHD 4.0. The FPGA
repository never had the relevant files, and the block controller also
never existed. This removes all the corresponding files from MPM, as
well as some references from makefiles.
Original-commit: ba00ff0cf5c0ced093e0be12b3006fe2f657a58a
USRP N230 is no longer supported starting with UHD 4, and thus, we can
remove it from the image manifest. This will no longer download N230
images when calling uhd_images_downloader from UHD 4.
Original-commit: f1f6d8eac52bfecd840ace95c2d357641ae3b09c
Currently, the build process copies the .twr and .syr files into the
build/ process after running ISE. For a succinct utilization report,
those files are not suitable, though, because they contain too much
information.
However, the build process already produces a custom, short utilization
report using grep and a summary of those reports. This patch modifies
the build such that the same output is copied into
a usrp_$product_fpga.rpt file, similar to our gen-3 devices.
Original-commit: 3a9f3204842d9851fef0e87b6b7d27261624a7fc
These pins control hardware-controlled fast-lock for tuning or
cycle-accurate gain control. This commit does nothing to these pins
other than expose them into the design and assign them to zero. This
does not change the current behaviour (the motherboard has pull-downs on
these pins, so they're low by default).
Original-commit: c891f2d8738bc1b73bb92d88623f4760f9e2bd1e
Before this change, only the channel 0 ATR state was sent to the
db_control module. For TwinRX, this had the disadvantage that when only
Channel 1 was used, the FP- and LED-GPIOs could not track the radio's
ATR state (e.g., no LED would light up in this case).
Note that unlike UHD 3, there is only one db_control module per slot.
There are therefore no options to map GPIOs to track the ATR state of an
individual channel.
Original-commit: f23ab72129041777bcd3357a1f4e37b29e62dd86
The script was previously only Python 2 compatible.
Python 2 support is now removed, so we don't maintain backwards
compatibility with Python 2.
This also fixes all linter warnings.
Original-commit: 6046e1a812ba2065d6ae13b4c4afdce8abc99d4f
- 2to3 was used to convert the Python scripts, except where the tool
choked and manual intervention was required
- All references to "python" where replaced with "python3"
- buffer() was replaced by memoryview()
Original-commit: ca68195b5d12c5410cfac8d459a0b0902c4c72c7
It was set to E320_HG, which is not a valid target, causing build errors
unless -t E320_1G was provided to rfnoc_image_builder.
Original-commit: 9ed42affcaa88e026cb4f82807e69b546ed30c8c
- Fixed some incorrect comments
- Fixed some missing wire declarations for internal NIC
- Fix wire declarations for GPIO (they were declared too late)
Original-commit: b18eaa75de2d1dcba2a1be0ee0b862a57e976cca
The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.
This commit also updates the license files and paths therein.
We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.
== Original Codebase and Rebasing ==
The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/
It can be used for bisecting, reference, and a more detailed history.
The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.
If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:
- Create a directory to store patches (this should be an empty
directory):
mkdir ~/patches
- Now make sure that your FPGA codebase is based on the same state as
the code that was merged:
cd src/fpga # Or wherever your FPGA code is stored
git rebase v4.0.0.0-pre-uhd-merge
Note: The rebase command may look slightly different depending on what
exactly you're trying to rebase.
- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:
git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches
Note: Make sure that only patches are stored in your output directory.
It should otherwise be empty. Make sure that you picked the correct
range of commits, and only commits you wanted to rebase were exported
as patch files.
- Go to the UHD repository and apply the patches:
cd src/uhd # Or wherever your UHD repository is stored
git am --directory fpga ~/patches/*
rm -rf ~/patches # This is for cleanup
== Contributors ==
The following people have contributed mainly to these files (this list
is not complete):
Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
