Martin Braun c98c7ab88d fpga: Remove dupes from DESIGN_SRCS ...

In the build Makefiles, this adds a function (uniq) which removes
duplicate entries from lists. We apply this to the DESIGN_SRCS passed
to the Vivado build process. This eliminates some warnings from
duplicate source files caused by redundantly referencing source files in
the Makefiles, possibly because they are listed in more than one source
file variable.


Original-commit: 1944263412d329d53b32a17e9735b79e59e319d7

2023-12-13 17:28:09 -06:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

sim

fpga: sim: Fix typo in clk_wait_f

2022-12-19 08:57:18 -06:00

tools

fpga: Remove dupes from DESIGN_SRCS

2023-12-13 17:28:09 -06:00

top

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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