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fpga: x300: sfpp: Fix warning about duplicate reg

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This removes a duplicate code section that causes build warnings. It
also references a wire that gets declared further down and the removed
and remaining code sections were incorrectly indented.


Original-commit: e8084eb4cb4ec6ff6476feb6e77ab3ea45dd969e
This commit is contained in:
Martin Braun
2024-01-04 10:24:05 -06:00
committed by Wade Fife
parent 27b06f86fb
commit df0b86f432
1 changed files with 9 additions and 19 deletions
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top/x300/x300_sfpp_io_core.v
+9 -19
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@@ -395,16 +395,6 @@ generate
.bist_checker_errors(bist_checker_errors)
);
reg mac_crit_err_latch;
always @(posedge bus_clk) begin
if (bus_rst | mac_clear) begin
mac_crit_err_latch <= 1'b0;
end else begin
if (mac_crit_err_bclk)
mac_crit_err_latch <= 1'b1;
end
end
assign m_axis_tuser = 4'd0;
wire set_stb;
@@ -449,15 +439,15 @@ generate
bist_lock_latency <= bist_lock_latency + 20'd1;
end
reg mac_crit_err_latch;
always @(posedge bus_clk) begin
if (bus_rst | mac_clear) begin
mac_crit_err_latch <= 1'b0;
end else begin
if (mac_crit_err_bclk)
mac_crit_err_latch <= 1'b1;
end
end
reg mac_crit_err_latch;
always @(posedge bus_clk) begin
if (bus_rst | mac_clear) begin
mac_crit_err_latch <= 1'b0;
end else begin
if (mac_crit_err_bclk)
mac_crit_err_latch <= 1'b1;
end
end
wire [31:0] core_status = {
6'h0, //[31:26]