56e84828fe057ffb136800112cff08ed3c17c853
Original-commit: adb88dbd1f996ed26bab654a9a059ea4f3ede823
The file is empty.
Languages
Verilog
42.5%
VHDL
13%
SystemVerilog
12%
HTML
11.1%
C
9.6%
Other
11.6%