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utils: image builder: Major update

Browse Source 
Most important effect of this change: rfnoc_image_builder is now
required to build bitfiles, 'make' alone won't suffice any longer!

This is a huge changeset to the image builder that combines multiple new
features:

- There no longer is a separate edge file for the static router. The
  static routes are generated as a Verilog parameter directly into the
  rfnoc_core_kernel (which is also modified).
- image_builder.py is split up into several smaller files. Code is moved
  into yaml_utils.py, and the new files grc.py, builder_config.py
- Generic module support is added. Aside from noc blocks and stream
  endpoints, we can now instantiate arbitrary modules (they also require
  a YAML description file).
- To enable such modules, resets are now also tracked the same way that
  clock domains are.
- The ImageBuilderConfig config object now more closes matches the
  original YAML file. The attributes 'clk_domain_con' and 'block_con' are
  removed. Instead, the attributes 'connections' and 'clk_domains' are
  sanitized and amended with extra annotations. The templates are
  updated to reflect this change.
- IO ports can now carry parameters, e.g., to have variable wire widths
  based on the configuration.
- Many Pylint warnings were resolved.
- Add inheritance support for image core YAML files.
  This allows image core files to (recursively) inherit from other image
  core files. To do so, simply put an 'inherit' entry at the top of the
  file:
```yaml
inherit: 'x410_radio_base.yml'
```
- The inheritance feature is used as part of the image core files.
- Image core and DTS files are now generated as a build artefact into
  the build directory. This requires the usage of rfnoc_image_builder to
  build images. As a consequence, it is no longer required to check in
  image core Verilog files.
- As another consequence, rfnoc_image_builder is required to build
  bitfiles!
- Image flavours are no longer defined through Makefiles, but purely
  from the image core YAML files.
- Remove all image core YAML files that do not generate a shipping
  image. Because of the inheritance feature and the requirement to use
  the image builder, it is trivial to add new YAML files.
- Add support for transport adapters through the YAML files. Before,
  transport adapters were inferred from the make target (e.g.,
  X410_X4_200 would have four 10GbE links based on the 'X4' substring).
  Now, transport adapters are defined via the image core YAML.
- This feature is currently only used (or can be used) by the X4xx
  series. Older devices may or may not be ported to allow custom
  transport adapters in the future.
- Add parameters to the BSP YAMLs and the devices itself. This allows
  setting global parameters in the image core files. For example, the
  X4x0 devices use this to decide if they instantiate DRAM channels.
- DTS includes and constraint files can now be requested by
  blocks/transport adapter through their YAML files. They do no longer
  need to be listed in the Makefile.
- Support for secure image cores. These are image cores that allow
  incorporating RFNoC blocks that require license keys and thus can't
  live in an open-source environment. This solution adds the option for
  secure image cores without touching the open source feature set.
- Add --reuse option to allow manual editing of generated artefacts
- Allow IO signatures from any module: until now IO signatures had to be
  defined in a single file (io_signatures). This file will persist. In
  addition each module can add its own IO signature as with the same
  format the core IO signatures placed under the top level key
  `io_signatures`.  IO signatures are still maintained in a global
  dictionary. The consequence is that they can be shared among
  independent modules as well as they have to have a globally unique
  name. The image builder will warn about detected name clashes for the
  signatures.
- As a consequence, some less commonly used IO signatures were moved to
  their corresponding module YAML files.

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Lars Amsel <lars.amsel@ni.com>


Original-commit: a98ce2621e2a2dc25535fc700b49bfcb00b8eb59
This commit is contained in:
Martin Braun
2024-06-11 10:20:07 +02:00
committed by Joerg Hofrichter
co-authored by Wade Fife Lars Amsel
parent 77d07a9714
commit 8669c68048
93 changed files with 1716 additions and 20268 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/rfnoc/blocks/rfnoc_block_license_check/Makefile
-4
View File
@@ -20,16 +20,12 @@ include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
# dependencies.
include $(LIB_DIR)/rfnoc/core/Makefile.srcs
include $(LIB_DIR)/rfnoc/utils/Makefile.srcs
include $(LIB_DIR)/sec/Makefile.srcs
include $(LIB_DIR)/hwutils/Makefile.srcs
include Makefile.srcs
DESIGN_SRCS += $(abspath \
$(RFNOC_CORE_SRCS) \
$(RFNOC_UTIL_SRCS) \
$(RFNOC_BLOCK_LICENSE_CHECK_SRCS) \
$(SEC_SRCS) \
$(HWUTILS_SRCS) \
)
#-------------------------------------------------
lib/rfnoc/blocks/rfnoc_block_license_check/Makefile.srcs
+6
View File
@@ -4,8 +4,14 @@
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(LIB_DIR)/sec/Makefile.srcs
include $(LIB_DIR)/hwutils/Makefile.srcs
RFNOC_BLOCK_LICENSE_CHECK_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/blocks/rfnoc_block_license_check/, \
noc_shell_license_check.v \
rfnoc_block_license_check_regs.vh \
rfnoc_block_license_check.v \
))
RFNOC_BLOCK_LICENSE_CHECK_SRCS += $(SEC_SRCS) $(HWUTILS_SRCS)
lib/rfnoc/core/rfnoc_core_kernel.v
+20 -4
View File
@@ -23,6 +23,8 @@
// transports are directly connected to SEPs
// - EDGE_TBL_FILE: The memory init file for the static connection
// adjacency list
// - EDGE_TBL: The adjacency list as a parameter. If EDGE_TBL_FILE is provided,
// this is ignored for backward compatibility.
//
// Signals:
// - chdr_aclk : The input CHDR clock (may be unbuffered if SAFE_START_CLKS=1)
@@ -50,7 +52,8 @@ module rfnoc_core_kernel #(
parameter [9:0] NUM_TRANSPORTS = 0,
parameter [11:0] NUM_EDGES = 0,
parameter [0:0] CHDR_XBAR_PRESENT = 1,
parameter EDGE_TBL_FILE = ""
parameter EDGE_TBL_FILE = "",
parameter [(NUM_EDGES*32)-1:0] EDGE_TBL = {NUM_EDGES{32'b0}}
)(
// Input clocks and resets
input wire chdr_aclk,
@@ -362,7 +365,7 @@ module rfnoc_core_kernel #(
// The BlkIndex is the port number of the block on the control crossbar amd the BlkPort is
// the index of the input or output port of the block.
generate if (EDGE_TBL_FILE == "" || NUM_EDGES == 0) begin
generate if ((EDGE_TBL_FILE == "" && EDGE_TBL == 0) || NUM_EDGES == 0) begin
// If no file is specified or if the number of edges is zero
// then just return zero for all transactions
always @(posedge core_ctrl_clk) begin
@@ -372,8 +375,21 @@ module rfnoc_core_kernel #(
end else begin
// Initialize ROM from file and read it during a reg transaction
reg [31:0] edge_tbl_rom[0:NUM_EDGES];
initial begin
$readmemh(EDGE_TBL_FILE, edge_tbl_rom, 0, NUM_EDGES);
if (EDGE_TBL_FILE != "") begin
initial begin
$readmemh(EDGE_TBL_FILE, edge_tbl_rom, 0, NUM_EDGES);
end
end if (EDGE_TBL == 0) begin
ERROR_edge_tbl_not_defined();
end else begin
integer edge_idx;
initial begin
edge_tbl_rom[0] = {20'b0, NUM_EDGES};
for (edge_idx = 1; edge_idx < NUM_EDGES + 1; edge_idx = edge_idx + 1) begin
edge_tbl_rom[edge_idx] = EDGE_TBL[(32*edge_idx)-1 -: 32];
end
end
end
always @(posedge core_ctrl_clk) begin
con_resp_ack <= (con_req_wr | con_req_rd);
tools/make/viv_preamble.mak
+4
View File
@@ -32,11 +32,15 @@ MAKEFILE_DIR = $(abspath .)
IP_BUILD_DIR ?= $(abspath ./build-ip/$(subst /,,$(PART_ID)))
BUILD_BASE_DIR ?= $(abspath .)
ifdef ARTIFACT_DIR
BUILD_DIR = $(abspath $(ARTIFACT_DIR))
else
ifdef NAME
BUILD_DIR = $(abspath $(BUILD_BASE_DIR)/build-$(NAME))
else
BUILD_DIR = $(abspath $(BUILD_BASE_DIR)/build)
endif
endif
# -------------------------------------------------------------------
top/e31x/Makefile
+2 -3
View File
@@ -38,11 +38,10 @@ endif
TOP ?= e31x
DEFAULT_IMAGE_CORE_FILE_E31X=e310_rfnoc_image_core.v
DEFAULT_EDGE_FILE_E31X=$(abspath e310_static_router.hex)
# vivado_build($1=Device, $2=Definitions)
vivado_build = make -f Makefile.e31x.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_E31X) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_E31X)
vivado_ip = make -f Makefile.e31x.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_E31X) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_E31X)
vivado_build = make -f Makefile.e31x.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_E31X)
vivado_ip = make -f Makefile.e31x.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_E31X)
# post_build($1=Device, $2=Option)
ifeq ($(TARGET),bin)
top/e31x/Makefile.e31x.inc
+2 -4
View File
@@ -48,7 +48,6 @@ include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
-include $(RFNOC_OOT_MAKEFILE_SRCS)
IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
EDGE_FILE ?= $(DEFAULT_EDGE_FILE)
##################################################
# Sources
@@ -64,7 +63,7 @@ TOP_SRCS += e31x.v
TOP_SRCS += e31x_core.v
TOP_SRCS += e31x_dram.v
TOP_SRCS += e310_io.v
TOP_SRCS += $(EDGE_FILE) $(IMAGE_CORE)
TOP_SRCS += $(IMAGE_CORE)
MB_XDC = \
e31x_pins.xdc \
e31x_timing.xdc
@@ -108,7 +107,6 @@ $(RFNOC_BLOCK_REPLAY_SRCS) \
$(RFNOC_BLOCK_EXAMPLE_SRCS) \
$(abspath $(MB_XDC))
EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
##################################################
@@ -116,7 +114,7 @@ IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
##################################################
.SECONDEXPANSION:
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF)
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_DEF)
# DESIGN_SRCS and VERILOG_DEFS must be defined
bin: .prereqs
top/e31x/e310_rfnoc_image_core.v
+33 -29
View File
@@ -39,27 +39,27 @@ module rfnoc_image_core #(
// IO ports /////////////////////////
// ctrlport
output wire [ 0:0] m_ctrlport_req_wr,
output wire [ 0:0] m_ctrlport_req_rd,
output wire m_ctrlport_req_wr,
output wire m_ctrlport_req_rd,
output wire [ 19:0] m_ctrlport_req_addr,
output wire [ 31:0] m_ctrlport_req_data,
output wire [ 3:0] m_ctrlport_req_byte_en,
output wire [ 0:0] m_ctrlport_req_has_time,
output wire m_ctrlport_req_has_time,
output wire [ 63:0] m_ctrlport_req_time,
input wire [ 0:0] m_ctrlport_resp_ack,
input wire m_ctrlport_resp_ack,
input wire [ 1:0] m_ctrlport_resp_status,
input wire [ 31:0] m_ctrlport_resp_data,
// time
input wire [ 63:0] radio_time,
// radio
input wire [1023:0] radio_rx_data,
input wire [ 31:0] radio_rx_stb,
output wire [ 31:0] radio_rx_running,
output wire [1023:0] radio_tx_data,
input wire [ 31:0] radio_tx_stb,
output wire [ 31:0] radio_tx_running,
input wire [ 63:0] radio_rx_data,
input wire [ 1:0] radio_rx_stb,
output wire [ 1:0] radio_rx_running,
output wire [ 63:0] radio_tx_data,
input wire [ 1:0] radio_tx_stb,
output wire [ 1:0] radio_tx_running,
// dram
input wire [ 0:0] axi_rst,
input wire axi_rst,
output wire [ 7:0] m_axi_awid,
output wire [ 383:0] m_axi_awaddr,
output wire [ 63:0] m_axi_awlen,
@@ -118,7 +118,6 @@ module rfnoc_image_core #(
input wire m_dma_tready
);
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
@@ -386,7 +385,12 @@ module rfnoc_image_core #(
.NUM_TRANSPORTS (1),
.NUM_EDGES (4),
.CHDR_XBAR_PRESENT (1),
.EDGE_TBL_FILE (EDGE_TBL_FILE)
.EDGE_TBL ({
{10'd03, 6'd01, 10'd02, 6'd00},
{10'd02, 6'd00, 10'd03, 6'd01},
{10'd03, 6'd00, 10'd01, 6'd00},
{10'd01, 6'd00, 10'd03, 6'd00}
})
) core_kernel_i (
.chdr_aclk (chdr_aclk),
.chdr_aclk_locked (1'b1),
@@ -430,31 +434,31 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire radio0_m_ctrlport_req_wr;
wire radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire radio0_m_ctrlport_req_has_time;
wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time
wire [ 63:0] radio0_radio_time;
// radio
wire [1023:0] radio0_radio_rx_data;
wire [ 31:0] radio0_radio_rx_stb;
wire [ 31:0] radio0_radio_rx_running;
wire [1023:0] radio0_radio_tx_data;
wire [ 31:0] radio0_radio_tx_stb;
wire [ 31:0] radio0_radio_tx_running;
wire [32*RADIO_NIPC*2-1:0] radio0_radio_rx_data;
wire [ 1:0] radio0_radio_rx_stb;
wire [ 1:0] radio0_radio_rx_running;
wire [32*RADIO_NIPC*2-1:0] radio0_radio_tx_data;
wire [ 1:0] radio0_radio_tx_stb;
wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (2),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2),
.NIPC (1),
.NIPC (RADIO_NIPC),
.ITEM_W (32),
.MTU (BLOCK_MTU)
) b_radio0_0 (
@@ -488,12 +492,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
);
@@ -530,7 +534,7 @@ module rfnoc_image_core #(
//---------------------------------------------------------------------------
// Clock Domains
// Clock Domains and Resets
//---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk;
top/e31x/e310_rfnoc_image_core.yml
+1
View File
@@ -30,6 +30,7 @@ noc_blocks:
block_desc: 'radio.yml' # Block device descriptor
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
# A list of all static connections in design
# ------------------------------------------
top/e31x/e310_static_router.hex
-5
View File
@@ -1,5 +0,0 @@
00000004
004000c0
00c00040
008000c1
00c10080
top/e320/Makefile
+2 -3
View File
@@ -41,11 +41,10 @@ endif
TOP ?= e320
DEFAULT_IMAGE_CORE_FILE_E320=e320_rfnoc_image_core.v
DEFAULT_EDGE_FILE_E320=$(abspath e320_static_router.hex)
# vivado_build($1=Device, $2=Definitions)
vivado_build = make -f Makefile.e320.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_$1)
vivado_ip = make -f Makefile.e320.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_$1)
vivado_build = make -f Makefile.e320.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1)
vivado_ip = make -f Makefile.e320.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1)
# post_build($1=Device, $2=Option)
ifeq ($(TARGET),bin)
top/e320/Makefile.e320.inc
+1 -3
View File
@@ -51,7 +51,6 @@ include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
-include $(RFNOC_OOT_MAKEFILE_SRCS)
IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
EDGE_FILE ?= $(DEFAULT_EDGE_FILE)
##################################################
# Sources
@@ -124,7 +123,6 @@ $(RFNOC_BLOCK_RADIO_SRCS) \
$(AXI4S_SV_SRCS) $(RFNOC_XPORT_SV_SRCS) \
$(abspath $(MB_XDC))
EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
##################################################
@@ -132,7 +130,7 @@ IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
##################################################
.SECONDEXPANSION:
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF)
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_DEF)
# DESIGN_SRCS and VERILOG_DEFS must be defined
bin: .prereqs
top/e320/e320_rfnoc_image_core.v
+55 -41
View File
@@ -40,27 +40,27 @@ module rfnoc_image_core #(
// IO ports /////////////////////////
// ctrlport
output wire [ 0:0] m_ctrlport_req_wr,
output wire [ 0:0] m_ctrlport_req_rd,
output wire m_ctrlport_req_wr,
output wire m_ctrlport_req_rd,
output wire [ 19:0] m_ctrlport_req_addr,
output wire [ 31:0] m_ctrlport_req_data,
output wire [ 3:0] m_ctrlport_req_byte_en,
output wire [ 0:0] m_ctrlport_req_has_time,
output wire m_ctrlport_req_has_time,
output wire [ 63:0] m_ctrlport_req_time,
input wire [ 0:0] m_ctrlport_resp_ack,
input wire m_ctrlport_resp_ack,
input wire [ 1:0] m_ctrlport_resp_status,
input wire [ 31:0] m_ctrlport_resp_data,
// time
input wire [ 63:0] radio_time,
// radio
input wire [1023:0] radio_rx_data,
input wire [ 31:0] radio_rx_stb,
output wire [ 31:0] radio_rx_running,
output wire [1023:0] radio_tx_data,
input wire [ 31:0] radio_tx_stb,
output wire [ 31:0] radio_tx_running,
input wire [ 63:0] radio_rx_data,
input wire [ 1:0] radio_rx_stb,
output wire [ 1:0] radio_rx_running,
output wire [ 63:0] radio_tx_data,
input wire [ 1:0] radio_tx_stb,
output wire [ 1:0] radio_tx_running,
// dram
input wire [ 0:0] axi_rst,
input wire axi_rst,
output wire [ 7:0] m_axi_awid,
output wire [ 383:0] m_axi_awaddr,
output wire [ 63:0] m_axi_awlen,
@@ -128,7 +128,6 @@ module rfnoc_image_core #(
input wire m_dma_tready
);
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
@@ -573,7 +572,20 @@ module rfnoc_image_core #(
.NUM_TRANSPORTS (2),
.NUM_EDGES (12),
.CHDR_XBAR_PRESENT (1),
.EDGE_TBL_FILE (EDGE_TBL_FILE)
.EDGE_TBL ({
{10'd08, 6'd01, 10'd04, 6'd00},
{10'd04, 6'd00, 10'd08, 6'd01},
{10'd08, 6'd00, 10'd03, 6'd00},
{10'd03, 6'd00, 10'd08, 6'd00},
{10'd06, 6'd01, 10'd02, 6'd00},
{10'd07, 6'd01, 10'd06, 6'd01},
{10'd05, 6'd01, 10'd07, 6'd01},
{10'd02, 6'd00, 10'd05, 6'd01},
{10'd06, 6'd00, 10'd01, 6'd00},
{10'd07, 6'd00, 10'd06, 6'd00},
{10'd05, 6'd00, 10'd07, 6'd00},
{10'd01, 6'd00, 10'd05, 6'd00}
})
) core_kernel_i (
.chdr_aclk (chdr_aclk),
.chdr_aclk_locked (1'b1),
@@ -616,6 +628,7 @@ module rfnoc_image_core #(
wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid;
wire m_duc0_out_1_tready, m_duc0_out_0_tready;
rfnoc_block_duc #(
.THIS_PORTID (2),
.CHDR_W (BLOCK_CHDR_W),
@@ -637,12 +650,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_duc0_out_1_tlast , m_duc0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_duc0_out_1_tvalid, m_duc0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_duc0_out_1_tready, m_duc0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_duc0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_duc0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_duc0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_duc0_ctrl_tready)
);
@@ -661,6 +674,7 @@ module rfnoc_image_core #(
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
rfnoc_block_ddc #(
.THIS_PORTID (3),
.CHDR_W (BLOCK_CHDR_W),
@@ -682,12 +696,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_ddc0_out_1_tlast , m_ddc0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_ddc0_out_1_tready, m_ddc0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_ddc0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_ddc0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_ddc0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready)
);
@@ -707,25 +721,25 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire radio0_m_ctrlport_req_wr;
wire radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire radio0_m_ctrlport_req_has_time;
wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time
wire [ 63:0] radio0_radio_time;
// radio
wire [1023:0] radio0_radio_rx_data;
wire [ 31:0] radio0_radio_rx_stb;
wire [ 31:0] radio0_radio_rx_running;
wire [1023:0] radio0_radio_tx_data;
wire [ 31:0] radio0_radio_tx_stb;
wire [ 31:0] radio0_radio_tx_running;
wire [32*1*2-1:0] radio0_radio_rx_data;
wire [ 1:0] radio0_radio_rx_stb;
wire [ 1:0] radio0_radio_rx_running;
wire [32*1*2-1:0] radio0_radio_tx_data;
wire [ 1:0] radio0_radio_tx_stb;
wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (4),
@@ -765,12 +779,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
);
@@ -790,7 +804,7 @@ module rfnoc_image_core #(
wire m_fifo0_out_1_tready, m_fifo0_out_0_tready;
// axi_ram
wire [ 0:0] fifo0_axi_rst;
wire fifo0_axi_rst;
wire [ 7:0] fifo0_m_axi_awid;
wire [ 383:0] fifo0_m_axi_awaddr;
wire [ 63:0] fifo0_m_axi_awlen;
@@ -907,12 +921,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_fifo0_out_1_tready, m_fifo0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_fifo0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_fifo0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_fifo0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready)
);
@@ -989,7 +1003,7 @@ module rfnoc_image_core #(
//---------------------------------------------------------------------------
// Clock Domains
// Clock Domains and Resets
//---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk;
top/e320/e320_static_router.hex
-13
View File
@@ -1,13 +0,0 @@
0000000C
00400140
014001c0
01c00180
01800040
00800141
014101c1
01c10181
01810080
00c00200
020000c0
01000201
02010100
top/n3xx/Makefile
+6 -6
View File
@@ -42,12 +42,12 @@ XQ_DEFS=SFP0_WR=1 QSFP_10GBE=1 BUILD_WR=1 BUILD_10G=1
AQ_DEFS=SFP0_10GBE=1 SFP1_10GBE=1 QSFP_AURORA=1 BUILD_10G=1 BUILD_AURORA=1 QSFP_LANES=4 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
# Defaults specific to the various targets:
N300_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n300_rfnoc_image_core.v) DEFAULT_EDGE_FILE=$(abspath n300_static_router.hex)
N310_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n310_rfnoc_image_core.v) DEFAULT_EDGE_FILE=$(abspath n310_static_router.hex)
N320_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n320_rfnoc_image_core.v) DEFAULT_EDGE_FILE=$(abspath n320_static_router.hex)
N300AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n300_bist_image_core.v) DEFAULT_EDGE_FILE=$(abspath n300_bist_static_router.hex)
N310AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n310_bist_image_core.v) DEFAULT_EDGE_FILE=$(abspath n310_bist_static_router.hex)
N320AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n320_bist_image_core.v) DEFAULT_EDGE_FILE=$(abspath n320_bist_static_router.hex)
N300_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n300_rfnoc_image_core.v)
N310_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n310_rfnoc_image_core.v)
N320_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n320_rfnoc_image_core.v)
N300AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n300_bist_image_core.v)
N310AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n310_bist_image_core.v)
N320AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n320_bist_image_core.v)
# Set build option (check RTL, run synthesis, or do a full build)
ifndef TARGET
top/n3xx/Makefile.n3xx.inc
+1 -3
View File
@@ -56,7 +56,6 @@ include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs
-include $(RFNOC_OOT_MAKEFILE_SRCS)
IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
EDGE_FILE ?= $(DEFAULT_EDGE_FILE)
##################################################
# Sources
@@ -146,7 +145,6 @@ $(RFNOC_BLOCK_RADIO_SRCS) \
$(RFNOC_BLOCK_REPLAY_SRCS) \
$(AXI4S_SV_SRCS) $(RFNOC_XPORT_SV_SRCS) \
EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
##################################################
@@ -154,7 +152,7 @@ IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
##################################################
.SECONDEXPANSION:
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF)
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_DEF)
# DESIGN_SRCS and VERILOG_DEFS must be defined
bin: .prereqs
top/n3xx/n300_bist_rfnoc_image_core.v
+41 -33
View File
@@ -42,27 +42,27 @@ module rfnoc_image_core #(
// IO ports /////////////////////////
// ctrlport_radio0
output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire m_ctrlport_radio0_req_wr,
output wire m_ctrlport_radio0_req_rd,
output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire m_ctrlport_radio0_req_has_time,
output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire m_ctrlport_radio0_resp_ack,
input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 31:0] m_ctrlport_radio0_resp_data,
// time
input wire [ 63:0] radio_time,
// radio0
input wire [1023:0] radio_rx_data_radio0,
input wire [ 31:0] radio_rx_stb_radio0,
output wire [ 31:0] radio_rx_running_radio0,
output wire [1023:0] radio_tx_data_radio0,
input wire [ 31:0] radio_tx_stb_radio0,
output wire [ 31:0] radio_tx_running_radio0,
input wire [ 63:0] radio_rx_data_radio0,
input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 1:0] radio_rx_running_radio0,
output wire [ 63:0] radio_tx_data_radio0,
input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 1:0] radio_tx_running_radio0,
// dram
input wire [ 0:0] axi_rst,
input wire axi_rst,
output wire [ 7:0] m_axi_awid,
output wire [ 383:0] m_axi_awaddr,
output wire [ 63:0] m_axi_awlen,
@@ -139,7 +139,6 @@ module rfnoc_image_core #(
input wire m_dma_tready
);
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
@@ -577,7 +576,16 @@ module rfnoc_image_core #(
.NUM_TRANSPORTS (3),
.NUM_EDGES (8),
.CHDR_XBAR_PRESENT (1),
.EDGE_TBL_FILE (EDGE_TBL_FILE)
.EDGE_TBL ({
{10'd06, 6'd01, 10'd04, 6'd00},
{10'd04, 6'd00, 10'd06, 6'd01},
{10'd06, 6'd00, 10'd03, 6'd00},
{10'd03, 6'd00, 10'd06, 6'd00},
{10'd05, 6'd01, 10'd02, 6'd00},
{10'd02, 6'd00, 10'd05, 6'd01},
{10'd05, 6'd00, 10'd01, 6'd00},
{10'd01, 6'd00, 10'd05, 6'd00}
})
) core_kernel_i (
.chdr_aclk (chdr_aclk),
.chdr_aclk_locked (1'b1),
@@ -621,25 +629,25 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire radio0_m_ctrlport_req_wr;
wire radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire radio0_m_ctrlport_req_has_time;
wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time
wire [ 63:0] radio0_radio_time;
// radio
wire [1023:0] radio0_radio_rx_data;
wire [ 31:0] radio0_radio_rx_stb;
wire [ 31:0] radio0_radio_rx_running;
wire [1023:0] radio0_radio_tx_data;
wire [ 31:0] radio0_radio_tx_stb;
wire [ 31:0] radio0_radio_tx_running;
wire [32*1*2-1:0] radio0_radio_rx_data;
wire [ 1:0] radio0_radio_rx_stb;
wire [ 1:0] radio0_radio_rx_running;
wire [32*1*2-1:0] radio0_radio_tx_data;
wire [ 1:0] radio0_radio_tx_stb;
wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (2),
@@ -679,12 +687,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
);
@@ -704,7 +712,7 @@ module rfnoc_image_core #(
wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready;
// axi_ram
wire [ 0:0] fifo0_axi_rst;
wire fifo0_axi_rst;
wire [ 7:0] fifo0_m_axi_awid;
wire [ 383:0] fifo0_m_axi_awaddr;
wire [ 63:0] fifo0_m_axi_awlen;
@@ -821,12 +829,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_fifo0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_fifo0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_fifo0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready)
);
@@ -891,7 +899,7 @@ module rfnoc_image_core #(
//---------------------------------------------------------------------------
// Clock Domains
// Clock Domains and Resets
//---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk;
top/n3xx/n300_bist_static_router.hex
-9
View File
@@ -1,9 +0,0 @@
00000008
00400140
01400040
00800141
01410080
00c00180
018000c0
01000181
01810100
top/n3xx/n300_rfnoc_image_core.v
+55 -41
View File
@@ -42,27 +42,27 @@ module rfnoc_image_core #(
// IO ports /////////////////////////
// ctrlport_radio0
output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire m_ctrlport_radio0_req_wr,
output wire m_ctrlport_radio0_req_rd,
output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire m_ctrlport_radio0_req_has_time,
output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire m_ctrlport_radio0_resp_ack,
input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 31:0] m_ctrlport_radio0_resp_data,
// time
input wire [ 63:0] radio_time,
// radio0
input wire [1023:0] radio_rx_data_radio0,
input wire [ 31:0] radio_rx_stb_radio0,
output wire [ 31:0] radio_rx_running_radio0,
output wire [1023:0] radio_tx_data_radio0,
input wire [ 31:0] radio_tx_stb_radio0,
output wire [ 31:0] radio_tx_running_radio0,
input wire [ 63:0] radio_rx_data_radio0,
input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 1:0] radio_rx_running_radio0,
output wire [ 63:0] radio_tx_data_radio0,
input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 1:0] radio_tx_running_radio0,
// dram
input wire [ 0:0] axi_rst,
input wire axi_rst,
output wire [ 7:0] m_axi_awid,
output wire [ 383:0] m_axi_awaddr,
output wire [ 63:0] m_axi_awlen,
@@ -139,7 +139,6 @@ module rfnoc_image_core #(
input wire m_dma_tready
);
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
@@ -585,7 +584,20 @@ module rfnoc_image_core #(
.NUM_TRANSPORTS (3),
.NUM_EDGES (12),
.CHDR_XBAR_PRESENT (1),
.EDGE_TBL_FILE (EDGE_TBL_FILE)
.EDGE_TBL ({
{10'd08, 6'd01, 10'd04, 6'd00},
{10'd04, 6'd00, 10'd08, 6'd01},
{10'd08, 6'd00, 10'd03, 6'd00},
{10'd03, 6'd00, 10'd08, 6'd00},
{10'd06, 6'd01, 10'd02, 6'd00},
{10'd07, 6'd01, 10'd06, 6'd01},
{10'd05, 6'd01, 10'd07, 6'd01},
{10'd02, 6'd00, 10'd05, 6'd01},
{10'd06, 6'd00, 10'd01, 6'd00},
{10'd07, 6'd00, 10'd06, 6'd00},
{10'd05, 6'd00, 10'd07, 6'd00},
{10'd01, 6'd00, 10'd05, 6'd00}
})
) core_kernel_i (
.chdr_aclk (chdr_aclk),
.chdr_aclk_locked (1'b1),
@@ -628,6 +640,7 @@ module rfnoc_image_core #(
wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid;
wire m_duc0_out_1_tready, m_duc0_out_0_tready;
rfnoc_block_duc #(
.THIS_PORTID (2),
.CHDR_W (BLOCK_CHDR_W),
@@ -649,12 +662,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_duc0_out_1_tlast , m_duc0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_duc0_out_1_tvalid, m_duc0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_duc0_out_1_tready, m_duc0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_duc0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_duc0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_duc0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_duc0_ctrl_tready)
);
@@ -673,6 +686,7 @@ module rfnoc_image_core #(
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
rfnoc_block_ddc #(
.THIS_PORTID (3),
.CHDR_W (BLOCK_CHDR_W),
@@ -694,12 +708,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_ddc0_out_1_tlast , m_ddc0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_ddc0_out_1_tready, m_ddc0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_ddc0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_ddc0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_ddc0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready)
);
@@ -719,25 +733,25 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire radio0_m_ctrlport_req_wr;
wire radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire radio0_m_ctrlport_req_has_time;
wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time
wire [ 63:0] radio0_radio_time;
// radio
wire [1023:0] radio0_radio_rx_data;
wire [ 31:0] radio0_radio_rx_stb;
wire [ 31:0] radio0_radio_rx_running;
wire [1023:0] radio0_radio_tx_data;
wire [ 31:0] radio0_radio_tx_stb;
wire [ 31:0] radio0_radio_tx_running;
wire [32*1*2-1:0] radio0_radio_rx_data;
wire [ 1:0] radio0_radio_rx_stb;
wire [ 1:0] radio0_radio_rx_running;
wire [32*1*2-1:0] radio0_radio_tx_data;
wire [ 1:0] radio0_radio_tx_stb;
wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (4),
@@ -777,12 +791,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
);
@@ -802,7 +816,7 @@ module rfnoc_image_core #(
wire m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram
wire [ 0:0] replay0_axi_rst;
wire replay0_axi_rst;
wire [ 7:0] replay0_m_axi_awid;
wire [ 383:0] replay0_m_axi_awaddr;
wire [ 63:0] replay0_m_axi_awlen;
@@ -914,12 +928,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_replay0_out_1_tready, m_replay0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_replay0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_replay0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_replay0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_replay0_ctrl_tready)
);
@@ -996,7 +1010,7 @@ module rfnoc_image_core #(
//---------------------------------------------------------------------------
// Clock Domains
// Clock Domains and Resets
//---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk;
top/n3xx/n300_static_router.hex
-13
View File
@@ -1,13 +0,0 @@
0000000C
00400140
014001c0
01c00180
01800040
00800141
014101c1
01c10181
01810080
00c00200
020000c0
01000201
02010100
top/n3xx/n310_bist_rfnoc_image_core.v
+69 -57
View File
@@ -42,45 +42,45 @@ module rfnoc_image_core #(
// IO ports /////////////////////////
// ctrlport_radio0
output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire m_ctrlport_radio0_req_wr,
output wire m_ctrlport_radio0_req_rd,
output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire m_ctrlport_radio0_req_has_time,
output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire m_ctrlport_radio0_resp_ack,
input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 31:0] m_ctrlport_radio0_resp_data,
// ctrlport_radio1
output wire [ 0:0] m_ctrlport_radio1_req_wr,
output wire [ 0:0] m_ctrlport_radio1_req_rd,
output wire m_ctrlport_radio1_req_wr,
output wire m_ctrlport_radio1_req_rd,
output wire [ 19:0] m_ctrlport_radio1_req_addr,
output wire [ 31:0] m_ctrlport_radio1_req_data,
output wire [ 3:0] m_ctrlport_radio1_req_byte_en,
output wire [ 0:0] m_ctrlport_radio1_req_has_time,
output wire m_ctrlport_radio1_req_has_time,
output wire [ 63:0] m_ctrlport_radio1_req_time,
input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire m_ctrlport_radio1_resp_ack,
input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 31:0] m_ctrlport_radio1_resp_data,
// time
input wire [ 63:0] radio_time,
// radio0
input wire [1023:0] radio_rx_data_radio0,
input wire [ 31:0] radio_rx_stb_radio0,
output wire [ 31:0] radio_rx_running_radio0,
output wire [1023:0] radio_tx_data_radio0,
input wire [ 31:0] radio_tx_stb_radio0,
output wire [ 31:0] radio_tx_running_radio0,
input wire [ 63:0] radio_rx_data_radio0,
input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 1:0] radio_rx_running_radio0,
output wire [ 63:0] radio_tx_data_radio0,
input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 1:0] radio_tx_running_radio0,
// radio1
input wire [1023:0] radio_rx_data_radio1,
input wire [ 31:0] radio_rx_stb_radio1,
output wire [ 31:0] radio_rx_running_radio1,
output wire [1023:0] radio_tx_data_radio1,
input wire [ 31:0] radio_tx_stb_radio1,
output wire [ 31:0] radio_tx_running_radio1,
input wire [ 63:0] radio_rx_data_radio1,
input wire [ 1:0] radio_rx_stb_radio1,
output wire [ 1:0] radio_rx_running_radio1,
output wire [ 63:0] radio_tx_data_radio1,
input wire [ 1:0] radio_tx_stb_radio1,
output wire [ 1:0] radio_tx_running_radio1,
// dram
input wire [ 0:0] axi_rst,
input wire axi_rst,
output wire [ 7:0] m_axi_awid,
output wire [ 383:0] m_axi_awaddr,
output wire [ 63:0] m_axi_awlen,
@@ -157,7 +157,6 @@ module rfnoc_image_core #(
input wire m_dma_tready
);
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
@@ -763,7 +762,20 @@ module rfnoc_image_core #(
.NUM_TRANSPORTS (3),
.NUM_EDGES (12),
.CHDR_XBAR_PRESENT (1),
.EDGE_TBL_FILE (EDGE_TBL_FILE)
.EDGE_TBL ({
{10'd09, 6'd01, 10'd06, 6'd00},
{10'd06, 6'd00, 10'd09, 6'd01},
{10'd09, 6'd00, 10'd05, 6'd00},
{10'd05, 6'd00, 10'd09, 6'd00},
{10'd08, 6'd01, 10'd04, 6'd00},
{10'd04, 6'd00, 10'd08, 6'd01},
{10'd08, 6'd00, 10'd03, 6'd00},
{10'd03, 6'd00, 10'd08, 6'd00},
{10'd07, 6'd01, 10'd02, 6'd00},
{10'd02, 6'd00, 10'd07, 6'd01},
{10'd07, 6'd00, 10'd01, 6'd00},
{10'd01, 6'd00, 10'd07, 6'd00}
})
) core_kernel_i (
.chdr_aclk (chdr_aclk),
.chdr_aclk_locked (1'b1),
@@ -807,25 +819,25 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire radio0_m_ctrlport_req_wr;
wire radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire radio0_m_ctrlport_req_has_time;
wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time
wire [ 63:0] radio0_radio_time;
// radio
wire [1023:0] radio0_radio_rx_data;
wire [ 31:0] radio0_radio_rx_stb;
wire [ 31:0] radio0_radio_rx_running;
wire [1023:0] radio0_radio_tx_data;
wire [ 31:0] radio0_radio_tx_stb;
wire [ 31:0] radio0_radio_tx_running;
wire [32*1*2-1:0] radio0_radio_rx_data;
wire [ 1:0] radio0_radio_rx_stb;
wire [ 1:0] radio0_radio_rx_running;
wire [32*1*2-1:0] radio0_radio_tx_data;
wire [ 1:0] radio0_radio_tx_stb;
wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (2),
@@ -865,12 +877,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
);
@@ -890,25 +902,25 @@ module rfnoc_image_core #(
wire m_radio1_out_1_tready, m_radio1_out_0_tready;
// ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 0:0] radio1_m_ctrlport_req_rd;
wire radio1_m_ctrlport_req_wr;
wire radio1_m_ctrlport_req_rd;
wire [ 19:0] radio1_m_ctrlport_req_addr;
wire [ 31:0] radio1_m_ctrlport_req_data;
wire [ 3:0] radio1_m_ctrlport_req_byte_en;
wire [ 0:0] radio1_m_ctrlport_req_has_time;
wire radio1_m_ctrlport_req_has_time;
wire [ 63:0] radio1_m_ctrlport_req_time;
wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire radio1_m_ctrlport_resp_ack;
wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 31:0] radio1_m_ctrlport_resp_data;
// time
wire [ 63:0] radio1_radio_time;
// radio
wire [1023:0] radio1_radio_rx_data;
wire [ 31:0] radio1_radio_rx_stb;
wire [ 31:0] radio1_radio_rx_running;
wire [1023:0] radio1_radio_tx_data;
wire [ 31:0] radio1_radio_tx_stb;
wire [ 31:0] radio1_radio_tx_running;
wire [32*1*2-1:0] radio1_radio_rx_data;
wire [ 1:0] radio1_radio_rx_stb;
wire [ 1:0] radio1_radio_rx_running;
wire [32*1*2-1:0] radio1_radio_tx_data;
wire [ 1:0] radio1_radio_tx_stb;
wire [ 1:0] radio1_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (3),
@@ -948,12 +960,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio1_out_1_tlast , m_radio1_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio1_out_1_tready, m_radio1_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio1_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio1_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio1_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio1_ctrl_tready)
);
@@ -973,7 +985,7 @@ module rfnoc_image_core #(
wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready;
// axi_ram
wire [ 0:0] fifo0_axi_rst;
wire fifo0_axi_rst;
wire [ 7:0] fifo0_m_axi_awid;
wire [ 383:0] fifo0_m_axi_awaddr;
wire [ 63:0] fifo0_m_axi_awlen;
@@ -1090,12 +1102,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_fifo0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_fifo0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_fifo0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready)
);
@@ -1180,7 +1192,7 @@ module rfnoc_image_core #(
//---------------------------------------------------------------------------
// Clock Domains
// Clock Domains and Resets
//---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk;
top/n3xx/n310_bist_static_router.hex
-13
View File
@@ -1,13 +0,0 @@
0000000C
004001c0
01c00040
008001c1
01c10080
00c00200
020000c0
01000201
02010100
01400240
02400140
01800241
02410180
top/n3xx/n310_rfnoc_image_core.v
+101 -73
View File
@@ -42,45 +42,45 @@ module rfnoc_image_core #(
// IO ports /////////////////////////
// ctrlport_radio0
output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire m_ctrlport_radio0_req_wr,
output wire m_ctrlport_radio0_req_rd,
output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire m_ctrlport_radio0_req_has_time,
output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire m_ctrlport_radio0_resp_ack,
input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 31:0] m_ctrlport_radio0_resp_data,
// ctrlport_radio1
output wire [ 0:0] m_ctrlport_radio1_req_wr,
output wire [ 0:0] m_ctrlport_radio1_req_rd,
output wire m_ctrlport_radio1_req_wr,
output wire m_ctrlport_radio1_req_rd,
output wire [ 19:0] m_ctrlport_radio1_req_addr,
output wire [ 31:0] m_ctrlport_radio1_req_data,
output wire [ 3:0] m_ctrlport_radio1_req_byte_en,
output wire [ 0:0] m_ctrlport_radio1_req_has_time,
output wire m_ctrlport_radio1_req_has_time,
output wire [ 63:0] m_ctrlport_radio1_req_time,
input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire m_ctrlport_radio1_resp_ack,
input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 31:0] m_ctrlport_radio1_resp_data,
// time
input wire [ 63:0] radio_time,
// radio0
input wire [1023:0] radio_rx_data_radio0,
input wire [ 31:0] radio_rx_stb_radio0,
output wire [ 31:0] radio_rx_running_radio0,
output wire [1023:0] radio_tx_data_radio0,
input wire [ 31:0] radio_tx_stb_radio0,
output wire [ 31:0] radio_tx_running_radio0,
input wire [ 63:0] radio_rx_data_radio0,
input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 1:0] radio_rx_running_radio0,
output wire [ 63:0] radio_tx_data_radio0,
input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 1:0] radio_tx_running_radio0,
// radio1
input wire [1023:0] radio_rx_data_radio1,
input wire [ 31:0] radio_rx_stb_radio1,
output wire [ 31:0] radio_rx_running_radio1,
output wire [1023:0] radio_tx_data_radio1,
input wire [ 31:0] radio_tx_stb_radio1,
output wire [ 31:0] radio_tx_running_radio1,
input wire [ 63:0] radio_rx_data_radio1,
input wire [ 1:0] radio_rx_stb_radio1,
output wire [ 1:0] radio_rx_running_radio1,
output wire [ 63:0] radio_tx_data_radio1,
input wire [ 1:0] radio_tx_stb_radio1,
output wire [ 1:0] radio_tx_running_radio1,
// dram
input wire [ 0:0] axi_rst,
input wire axi_rst,
output wire [ 7:0] m_axi_awid,
output wire [ 383:0] m_axi_awaddr,
output wire [ 63:0] m_axi_awlen,
@@ -157,7 +157,6 @@ module rfnoc_image_core #(
input wire m_dma_tready
);
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
@@ -943,7 +942,32 @@ module rfnoc_image_core #(
.NUM_TRANSPORTS (3),
.NUM_EDGES (24),
.CHDR_XBAR_PRESENT (1),
.EDGE_TBL_FILE (EDGE_TBL_FILE)
.EDGE_TBL ({
{10'd15, 6'd03, 10'd08, 6'd00},
{10'd08, 6'd00, 10'd15, 6'd03},
{10'd15, 6'd02, 10'd07, 6'd00},
{10'd07, 6'd00, 10'd15, 6'd02},
{10'd15, 6'd01, 10'd06, 6'd00},
{10'd06, 6'd00, 10'd15, 6'd01},
{10'd15, 6'd00, 10'd05, 6'd00},
{10'd05, 6'd00, 10'd15, 6'd00},
{10'd13, 6'd01, 10'd04, 6'd00},
{10'd14, 6'd01, 10'd13, 6'd01},
{10'd12, 6'd01, 10'd14, 6'd01},
{10'd04, 6'd00, 10'd12, 6'd01},
{10'd13, 6'd00, 10'd03, 6'd00},
{10'd14, 6'd00, 10'd13, 6'd00},
{10'd12, 6'd00, 10'd14, 6'd00},
{10'd03, 6'd00, 10'd12, 6'd00},
{10'd10, 6'd01, 10'd02, 6'd00},
{10'd11, 6'd01, 10'd10, 6'd01},
{10'd09, 6'd01, 10'd11, 6'd01},
{10'd02, 6'd00, 10'd09, 6'd01},
{10'd10, 6'd00, 10'd01, 6'd00},
{10'd11, 6'd00, 10'd10, 6'd00},
{10'd09, 6'd00, 10'd11, 6'd00},
{10'd01, 6'd00, 10'd09, 6'd00}
})
) core_kernel_i (
.chdr_aclk (chdr_aclk),
.chdr_aclk_locked (1'b1),
@@ -986,6 +1010,7 @@ module rfnoc_image_core #(
wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid;
wire m_duc0_out_1_tready, m_duc0_out_0_tready;
rfnoc_block_duc #(
.THIS_PORTID (2),
.CHDR_W (BLOCK_CHDR_W),
@@ -1007,12 +1032,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_duc0_out_1_tlast , m_duc0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_duc0_out_1_tvalid, m_duc0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_duc0_out_1_tready, m_duc0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_duc0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_duc0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_duc0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_duc0_ctrl_tready)
);
@@ -1031,6 +1056,7 @@ module rfnoc_image_core #(
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
rfnoc_block_ddc #(
.THIS_PORTID (3),
.CHDR_W (BLOCK_CHDR_W),
@@ -1052,12 +1078,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_ddc0_out_1_tlast , m_ddc0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_ddc0_out_1_tready, m_ddc0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_ddc0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_ddc0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_ddc0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready)
);
@@ -1077,25 +1103,25 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire radio0_m_ctrlport_req_wr;
wire radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire radio0_m_ctrlport_req_has_time;
wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time
wire [ 63:0] radio0_radio_time;
// radio
wire [1023:0] radio0_radio_rx_data;
wire [ 31:0] radio0_radio_rx_stb;
wire [ 31:0] radio0_radio_rx_running;
wire [1023:0] radio0_radio_tx_data;
wire [ 31:0] radio0_radio_tx_stb;
wire [ 31:0] radio0_radio_tx_running;
wire [32*1*2-1:0] radio0_radio_rx_data;
wire [ 1:0] radio0_radio_rx_stb;
wire [ 1:0] radio0_radio_rx_running;
wire [32*1*2-1:0] radio0_radio_tx_data;
wire [ 1:0] radio0_radio_tx_stb;
wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (4),
@@ -1135,12 +1161,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
);
@@ -1159,6 +1185,7 @@ module rfnoc_image_core #(
wire m_duc1_out_1_tvalid, m_duc1_out_0_tvalid;
wire m_duc1_out_1_tready, m_duc1_out_0_tready;
rfnoc_block_duc #(
.THIS_PORTID (5),
.CHDR_W (BLOCK_CHDR_W),
@@ -1180,12 +1207,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_duc1_out_1_tlast , m_duc1_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_duc1_out_1_tvalid, m_duc1_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_duc1_out_1_tready, m_duc1_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_duc1_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_duc1_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_duc1_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_duc1_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_duc1_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_duc1_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_duc1_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_duc1_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_duc1_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_duc1_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_duc1_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_duc1_ctrl_tready)
);
@@ -1204,6 +1231,7 @@ module rfnoc_image_core #(
wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid;
wire m_ddc1_out_1_tready, m_ddc1_out_0_tready;
rfnoc_block_ddc #(
.THIS_PORTID (6),
.CHDR_W (BLOCK_CHDR_W),
@@ -1225,12 +1253,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_ddc1_out_1_tlast , m_ddc1_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_ddc1_out_1_tready, m_ddc1_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_ddc1_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_ddc1_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_ddc1_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_ddc1_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_ddc1_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_ddc1_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_ddc1_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_ddc1_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_ddc1_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_ddc1_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_ddc1_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_ddc1_ctrl_tready)
);
@@ -1250,25 +1278,25 @@ module rfnoc_image_core #(
wire m_radio1_out_1_tready, m_radio1_out_0_tready;
// ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 0:0] radio1_m_ctrlport_req_rd;
wire radio1_m_ctrlport_req_wr;
wire radio1_m_ctrlport_req_rd;
wire [ 19:0] radio1_m_ctrlport_req_addr;
wire [ 31:0] radio1_m_ctrlport_req_data;
wire [ 3:0] radio1_m_ctrlport_req_byte_en;
wire [ 0:0] radio1_m_ctrlport_req_has_time;
wire radio1_m_ctrlport_req_has_time;
wire [ 63:0] radio1_m_ctrlport_req_time;
wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire radio1_m_ctrlport_resp_ack;
wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 31:0] radio1_m_ctrlport_resp_data;
// time
wire [ 63:0] radio1_radio_time;
// radio
wire [1023:0] radio1_radio_rx_data;
wire [ 31:0] radio1_radio_rx_stb;
wire [ 31:0] radio1_radio_rx_running;
wire [1023:0] radio1_radio_tx_data;
wire [ 31:0] radio1_radio_tx_stb;
wire [ 31:0] radio1_radio_tx_running;
wire [32*1*2-1:0] radio1_radio_rx_data;
wire [ 1:0] radio1_radio_rx_stb;
wire [ 1:0] radio1_radio_rx_running;
wire [32*1*2-1:0] radio1_radio_tx_data;
wire [ 1:0] radio1_radio_tx_stb;
wire [ 1:0] radio1_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (7),
@@ -1308,12 +1336,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio1_out_1_tlast , m_radio1_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio1_out_1_tready, m_radio1_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio1_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio1_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio1_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio1_ctrl_tready)
);
@@ -1333,7 +1361,7 @@ module rfnoc_image_core #(
wire m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram
wire [ 0:0] replay0_axi_rst;
wire replay0_axi_rst;
wire [ 7:0] replay0_m_axi_awid;
wire [ 383:0] replay0_m_axi_awaddr;
wire [ 63:0] replay0_m_axi_awlen;
@@ -1445,12 +1473,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_replay0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_replay0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_replay0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_replay0_ctrl_tready)
);
@@ -1587,7 +1615,7 @@ module rfnoc_image_core #(
//---------------------------------------------------------------------------
// Clock Domains
// Clock Domains and Resets
//---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk;
top/n3xx/n310_static_router.hex
-25
View File
@@ -1,25 +0,0 @@
00000018
00400240
024002c0
02c00280
02800040
00800241
024102c1
02c10281
02810080
00c00300
03000380
03800340
034000c0
01000301
03010381
03810341
03410100
014003c0
03c00140
018003c1
03c10180
01c003c2
03c201c0
020003c3
03c30200
top/n3xx/n320_bist_rfnoc_image_core.v
+65 -57
View File
@@ -42,45 +42,45 @@ module rfnoc_image_core #(
// IO ports /////////////////////////
// ctrlport_radio0
output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire m_ctrlport_radio0_req_wr,
output wire m_ctrlport_radio0_req_rd,
output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire m_ctrlport_radio0_req_has_time,
output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire m_ctrlport_radio0_resp_ack,
input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 31:0] m_ctrlport_radio0_resp_data,
// ctrlport_radio1
output wire [ 0:0] m_ctrlport_radio1_req_wr,
output wire [ 0:0] m_ctrlport_radio1_req_rd,
output wire m_ctrlport_radio1_req_wr,
output wire m_ctrlport_radio1_req_rd,
output wire [ 19:0] m_ctrlport_radio1_req_addr,
output wire [ 31:0] m_ctrlport_radio1_req_data,
output wire [ 3:0] m_ctrlport_radio1_req_byte_en,
output wire [ 0:0] m_ctrlport_radio1_req_has_time,
output wire m_ctrlport_radio1_req_has_time,
output wire [ 63:0] m_ctrlport_radio1_req_time,
input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire m_ctrlport_radio1_resp_ack,
input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 31:0] m_ctrlport_radio1_resp_data,
// time
input wire [ 63:0] radio_time,
// radio0
input wire [1023:0] radio_rx_data_radio0,
input wire [ 31:0] radio_rx_stb_radio0,
output wire [ 31:0] radio_rx_running_radio0,
output wire [1023:0] radio_tx_data_radio0,
input wire [ 31:0] radio_tx_stb_radio0,
output wire [ 31:0] radio_tx_running_radio0,
input wire [ 63:0] radio_rx_data_radio0,
input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 1:0] radio_rx_running_radio0,
output wire [ 63:0] radio_tx_data_radio0,
input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 1:0] radio_tx_running_radio0,
// radio1
input wire [1023:0] radio_rx_data_radio1,
input wire [ 31:0] radio_rx_stb_radio1,
output wire [ 31:0] radio_rx_running_radio1,
output wire [1023:0] radio_tx_data_radio1,
input wire [ 31:0] radio_tx_stb_radio1,
output wire [ 31:0] radio_tx_running_radio1,
input wire [ 63:0] radio_rx_data_radio1,
input wire [ 1:0] radio_rx_stb_radio1,
output wire [ 1:0] radio_rx_running_radio1,
output wire [ 63:0] radio_tx_data_radio1,
input wire [ 1:0] radio_tx_stb_radio1,
output wire [ 1:0] radio_tx_running_radio1,
// dram
input wire [ 0:0] axi_rst,
input wire axi_rst,
output wire [ 7:0] m_axi_awid,
output wire [ 383:0] m_axi_awaddr,
output wire [ 63:0] m_axi_awlen,
@@ -157,7 +157,6 @@ module rfnoc_image_core #(
input wire m_dma_tready
);
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
@@ -599,7 +598,16 @@ module rfnoc_image_core #(
.NUM_TRANSPORTS (3),
.NUM_EDGES (8),
.CHDR_XBAR_PRESENT (1),
.EDGE_TBL_FILE (EDGE_TBL_FILE)
.EDGE_TBL ({
{10'd07, 6'd01, 10'd04, 6'd00},
{10'd04, 6'd00, 10'd07, 6'd01},
{10'd07, 6'd00, 10'd03, 6'd00},
{10'd03, 6'd00, 10'd07, 6'd00},
{10'd06, 6'd00, 10'd02, 6'd00},
{10'd02, 6'd00, 10'd06, 6'd00},
{10'd05, 6'd00, 10'd01, 6'd00},
{10'd01, 6'd00, 10'd05, 6'd00}
})
) core_kernel_i (
.chdr_aclk (chdr_aclk),
.chdr_aclk_locked (1'b1),
@@ -643,25 +651,25 @@ module rfnoc_image_core #(
wire m_radio0_out_0_tready;
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire radio0_m_ctrlport_req_wr;
wire radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire radio0_m_ctrlport_req_has_time;
wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time
wire [ 63:0] radio0_radio_time;
// radio
wire [1023:0] radio0_radio_rx_data;
wire [ 31:0] radio0_radio_rx_stb;
wire [ 31:0] radio0_radio_rx_running;
wire [1023:0] radio0_radio_tx_data;
wire [ 31:0] radio0_radio_tx_stb;
wire [ 31:0] radio0_radio_tx_running;
wire [32*1*1-1:0] radio0_radio_rx_data;
wire radio0_radio_rx_stb;
wire radio0_radio_rx_running;
wire [32*1*1-1:0] radio0_radio_tx_data;
wire radio0_radio_tx_stb;
wire radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (2),
@@ -701,12 +709,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
);
@@ -726,25 +734,25 @@ module rfnoc_image_core #(
wire m_radio1_out_0_tready;
// ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 0:0] radio1_m_ctrlport_req_rd;
wire radio1_m_ctrlport_req_wr;
wire radio1_m_ctrlport_req_rd;
wire [ 19:0] radio1_m_ctrlport_req_addr;
wire [ 31:0] radio1_m_ctrlport_req_data;
wire [ 3:0] radio1_m_ctrlport_req_byte_en;
wire [ 0:0] radio1_m_ctrlport_req_has_time;
wire radio1_m_ctrlport_req_has_time;
wire [ 63:0] radio1_m_ctrlport_req_time;
wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire radio1_m_ctrlport_resp_ack;
wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 31:0] radio1_m_ctrlport_resp_data;
// time
wire [ 63:0] radio1_radio_time;
// radio
wire [1023:0] radio1_radio_rx_data;
wire [ 31:0] radio1_radio_rx_stb;
wire [ 31:0] radio1_radio_rx_running;
wire [1023:0] radio1_radio_tx_data;
wire [ 31:0] radio1_radio_tx_stb;
wire [ 31:0] radio1_radio_tx_running;
wire [32*1*1-1:0] radio1_radio_rx_data;
wire radio1_radio_rx_stb;
wire radio1_radio_rx_running;
wire [32*1*1-1:0] radio1_radio_tx_data;
wire radio1_radio_tx_stb;
wire radio1_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (3),
@@ -784,12 +792,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio1_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio1_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio1_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio1_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio1_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio1_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio1_ctrl_tready)
);
@@ -809,7 +817,7 @@ module rfnoc_image_core #(
wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready;
// axi_ram
wire [ 0:0] fifo0_axi_rst;
wire fifo0_axi_rst;
wire [ 7:0] fifo0_m_axi_awid;
wire [ 383:0] fifo0_m_axi_awaddr;
wire [ 63:0] fifo0_m_axi_awlen;
@@ -926,12 +934,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_fifo0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_fifo0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_fifo0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready)
);
@@ -996,7 +1004,7 @@ module rfnoc_image_core #(
//---------------------------------------------------------------------------
// Clock Domains
// Clock Domains and Resets
//---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk;
top/n3xx/n320_bist_static_router.hex
-9
View File
@@ -1,9 +0,0 @@
00000008
00400140
01400040
00800180
01800080
00c001c0
01c000c0
010001c1
01c10100
top/n3xx/n320_rfnoc_image_core.v
+89 -73
View File
@@ -42,45 +42,45 @@ module rfnoc_image_core #(
// IO ports /////////////////////////
// ctrlport_radio0
output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire m_ctrlport_radio0_req_wr,
output wire m_ctrlport_radio0_req_rd,
output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire m_ctrlport_radio0_req_has_time,
output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire m_ctrlport_radio0_resp_ack,
input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 31:0] m_ctrlport_radio0_resp_data,
// ctrlport_radio1
output wire [ 0:0] m_ctrlport_radio1_req_wr,
output wire [ 0:0] m_ctrlport_radio1_req_rd,
output wire m_ctrlport_radio1_req_wr,
output wire m_ctrlport_radio1_req_rd,
output wire [ 19:0] m_ctrlport_radio1_req_addr,
output wire [ 31:0] m_ctrlport_radio1_req_data,
output wire [ 3:0] m_ctrlport_radio1_req_byte_en,
output wire [ 0:0] m_ctrlport_radio1_req_has_time,
output wire m_ctrlport_radio1_req_has_time,
output wire [ 63:0] m_ctrlport_radio1_req_time,
input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire m_ctrlport_radio1_resp_ack,
input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 31:0] m_ctrlport_radio1_resp_data,
// time
input wire [ 63:0] radio_time,
// radio0
input wire [1023:0] radio_rx_data_radio0,
input wire [ 31:0] radio_rx_stb_radio0,
output wire [ 31:0] radio_rx_running_radio0,
output wire [1023:0] radio_tx_data_radio0,
input wire [ 31:0] radio_tx_stb_radio0,
output wire [ 31:0] radio_tx_running_radio0,
input wire [ 63:0] radio_rx_data_radio0,
input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 1:0] radio_rx_running_radio0,
output wire [ 63:0] radio_tx_data_radio0,
input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 1:0] radio_tx_running_radio0,
// radio1
input wire [1023:0] radio_rx_data_radio1,
input wire [ 31:0] radio_rx_stb_radio1,
output wire [ 31:0] radio_rx_running_radio1,
output wire [1023:0] radio_tx_data_radio1,
input wire [ 31:0] radio_tx_stb_radio1,
output wire [ 31:0] radio_tx_running_radio1,
input wire [ 63:0] radio_rx_data_radio1,
input wire [ 1:0] radio_rx_stb_radio1,
output wire [ 1:0] radio_rx_running_radio1,
output wire [ 63:0] radio_tx_data_radio1,
input wire [ 1:0] radio_tx_stb_radio1,
output wire [ 1:0] radio_tx_running_radio1,
// dram
input wire [ 0:0] axi_rst,
input wire axi_rst,
output wire [ 7:0] m_axi_awid,
output wire [ 383:0] m_axi_awaddr,
output wire [ 63:0] m_axi_awlen,
@@ -157,7 +157,6 @@ module rfnoc_image_core #(
input wire m_dma_tready
);
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
@@ -615,7 +614,20 @@ module rfnoc_image_core #(
.NUM_TRANSPORTS (3),
.NUM_EDGES (12),
.CHDR_XBAR_PRESENT (1),
.EDGE_TBL_FILE (EDGE_TBL_FILE)
.EDGE_TBL ({
{10'd11, 6'd01, 10'd04, 6'd00},
{10'd04, 6'd00, 10'd11, 6'd01},
{10'd11, 6'd00, 10'd03, 6'd00},
{10'd03, 6'd00, 10'd11, 6'd00},
{10'd09, 6'd00, 10'd02, 6'd00},
{10'd10, 6'd00, 10'd09, 6'd00},
{10'd08, 6'd00, 10'd10, 6'd00},
{10'd02, 6'd00, 10'd08, 6'd00},
{10'd06, 6'd00, 10'd01, 6'd00},
{10'd07, 6'd00, 10'd06, 6'd00},
{10'd05, 6'd00, 10'd07, 6'd00},
{10'd01, 6'd00, 10'd05, 6'd00}
})
) core_kernel_i (
.chdr_aclk (chdr_aclk),
.chdr_aclk_locked (1'b1),
@@ -658,6 +670,7 @@ module rfnoc_image_core #(
wire m_duc0_out_0_tvalid;
wire m_duc0_out_0_tready;
rfnoc_block_duc #(
.THIS_PORTID (2),
.CHDR_W (BLOCK_CHDR_W),
@@ -679,12 +692,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_duc0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_duc0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_duc0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_duc0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_duc0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_duc0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_duc0_ctrl_tready)
);
@@ -703,6 +716,7 @@ module rfnoc_image_core #(
wire m_ddc0_out_0_tvalid;
wire m_ddc0_out_0_tready;
rfnoc_block_ddc #(
.THIS_PORTID (3),
.CHDR_W (BLOCK_CHDR_W),
@@ -724,12 +738,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_ddc0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_ddc0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_ddc0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_ddc0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_ddc0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_ddc0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready)
);
@@ -749,25 +763,25 @@ module rfnoc_image_core #(
wire m_radio0_out_0_tready;
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire radio0_m_ctrlport_req_wr;
wire radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire radio0_m_ctrlport_req_has_time;
wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time
wire [ 63:0] radio0_radio_time;
// radio
wire [1023:0] radio0_radio_rx_data;
wire [ 31:0] radio0_radio_rx_stb;
wire [ 31:0] radio0_radio_rx_running;
wire [1023:0] radio0_radio_tx_data;
wire [ 31:0] radio0_radio_tx_stb;
wire [ 31:0] radio0_radio_tx_running;
wire [32*1*1-1:0] radio0_radio_rx_data;
wire radio0_radio_rx_stb;
wire radio0_radio_rx_running;
wire [32*1*1-1:0] radio0_radio_tx_data;
wire radio0_radio_tx_stb;
wire radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (4),
@@ -807,12 +821,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
);
@@ -831,6 +845,7 @@ module rfnoc_image_core #(
wire m_duc1_out_0_tvalid;
wire m_duc1_out_0_tready;
rfnoc_block_duc #(
.THIS_PORTID (5),
.CHDR_W (BLOCK_CHDR_W),
@@ -852,12 +867,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_duc1_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_duc1_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_duc1_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_duc1_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_duc1_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_duc1_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_duc1_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_duc1_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_duc1_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_duc1_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_duc1_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_duc1_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_duc1_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_duc1_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_duc1_ctrl_tready)
);
@@ -876,6 +891,7 @@ module rfnoc_image_core #(
wire m_ddc1_out_0_tvalid;
wire m_ddc1_out_0_tready;
rfnoc_block_ddc #(
.THIS_PORTID (6),
.CHDR_W (BLOCK_CHDR_W),
@@ -897,12 +913,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_ddc1_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_ddc1_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_ddc1_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_ddc1_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_ddc1_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_ddc1_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_ddc1_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_ddc1_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_ddc1_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_ddc1_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_ddc1_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_ddc1_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_ddc1_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_ddc1_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_ddc1_ctrl_tready)
);
@@ -922,25 +938,25 @@ module rfnoc_image_core #(
wire m_radio1_out_0_tready;
// ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 0:0] radio1_m_ctrlport_req_rd;
wire radio1_m_ctrlport_req_wr;
wire radio1_m_ctrlport_req_rd;
wire [ 19:0] radio1_m_ctrlport_req_addr;
wire [ 31:0] radio1_m_ctrlport_req_data;
wire [ 3:0] radio1_m_ctrlport_req_byte_en;
wire [ 0:0] radio1_m_ctrlport_req_has_time;
wire radio1_m_ctrlport_req_has_time;
wire [ 63:0] radio1_m_ctrlport_req_time;
wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire radio1_m_ctrlport_resp_ack;
wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 31:0] radio1_m_ctrlport_resp_data;
// time
wire [ 63:0] radio1_radio_time;
// radio
wire [1023:0] radio1_radio_rx_data;
wire [ 31:0] radio1_radio_rx_stb;
wire [ 31:0] radio1_radio_rx_running;
wire [1023:0] radio1_radio_tx_data;
wire [ 31:0] radio1_radio_tx_stb;
wire [ 31:0] radio1_radio_tx_running;
wire [32*1*1-1:0] radio1_radio_rx_data;
wire radio1_radio_rx_stb;
wire radio1_radio_rx_running;
wire [32*1*1-1:0] radio1_radio_tx_data;
wire radio1_radio_tx_stb;
wire radio1_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (7),
@@ -980,12 +996,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio1_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio1_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio1_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio1_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio1_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio1_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio1_ctrl_tready)
);
@@ -1005,7 +1021,7 @@ module rfnoc_image_core #(
wire m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram
wire [ 0:0] replay0_axi_rst;
wire replay0_axi_rst;
wire [ 7:0] replay0_m_axi_awid;
wire [ 383:0] replay0_m_axi_awaddr;
wire [ 63:0] replay0_m_axi_awlen;
@@ -1117,12 +1133,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_replay0_out_1_tready, m_replay0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_replay0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_replay0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_replay0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_replay0_ctrl_tready)
);
@@ -1199,7 +1215,7 @@ module rfnoc_image_core #(
//---------------------------------------------------------------------------
// Clock Domains
// Clock Domains and Resets
//---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk;
top/n3xx/n320_static_router.hex
-13
View File
@@ -1,13 +0,0 @@
0000000C
00400140
014001c0
01c00180
01800040
00800200
02000280
02800240
02400080
00c002c0
02c000c0
010002c1
02c10100
top/x300/Makefile
+10 -13
View File
@@ -28,6 +28,8 @@ BUILD_OUTPUT_DIR ?= $(BUILD_BASE_DIR)/build
# Initialize a build seed. This can be changed to randomly affect build results.
BUILD_SEED ?= 0
# The image core name is something like 'usrp_x310_fpga_XG'
IMAGE_CORE_NAME ?= usrp_fpga
GIGE_DEFS=BUILD_1G=1 SFP0_1GBE=1 SFP1_1GBE=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
HG_DEFS=BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
@@ -49,27 +51,22 @@ ifndef TARGET
endif
TOP ?= x300
DEFAULT_IMAGE_CORE_FILE_X300=x300_rfnoc_image_core.v
DEFAULT_IMAGE_CORE_FILE_X310=x310_rfnoc_image_core.v
DEFAULT_EDGE_FILE_X300=$(abspath x300_static_router.hex)
DEFAULT_EDGE_FILE_X310=$(abspath x310_static_router.hex)
# vivado_build($1=Device, $2=Definitions)
vivado_build = make -f Makefile.x300.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_$1)
vivado_ip = make -f Makefile.x300.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_$1)
vivado_build = make -f Makefile.x300.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
vivado_ip = make -f Makefile.x300.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
# post_build($1=Device, $2=Option)
ifeq ($(TARGET),bin)
post_build = @\
mkdir -p $(BUILD_OUTPUT_DIR); \
echo "Exporting bitstream files..."; \
cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/x300.bin $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bin; \
cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/x300.bit $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
cp $(ARTIFACT_DIR)/x300.bin $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bin; \
cp $(ARTIFACT_DIR)/x300.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
echo "Generating LVBITX..."; \
$(CREATE_LVBITX) --input-bin=$(BUILD_BASE_DIR)/build-$(1)_$(2)/x300.bin --output-lvbitx=$(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).lvbitx --device="USRP $(1)" x3x0_base.lvbitx; \
$(CREATE_LVBITX) --input-bin=$(ARTIFACT_DIR)/x300.bin --output-lvbitx=$(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).lvbitx --device="USRP $(1)" x3x0_base.lvbitx; \
cp -f x3x0_base.lvbitx $(BUILD_OUTPUT_DIR)/`echo $(1) | tr A-Z a-z`.lvbitx_base; \
echo "Exporting build report..."; \
cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
cp $(ARTIFACT_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
echo "Build DONE ... $(1)_$(2)";
else
post_build = @echo "Skipping bitfile export."
@@ -141,13 +138,13 @@ X300_XA: X300_IP
clean: ##Clean up all target build outputs.
@echo "Cleaning targets..."
@rm -rf $(BUILD_BASE_DIR)/build-X3*_*
@rm -rf $(BUILD_BASE_DIR)/build-X3*_* $(BUILD_BASE_DIR)/build-x3*
@rm -rf $(BUILD_OUTPUT_DIR)
cleanall: ##Clean up all target and ip build outputs.
@echo "Cleaning targets and IP..."
@rm -rf build-ip
@rm -rf $(BUILD_BASE_DIR)/build-X3*_*
@rm -rf $(BUILD_BASE_DIR)/build-X3*_* $(BUILD_BASE_DIR)/build-x3*
@rm -rf $(BUILD_OUTPUT_DIR)
help: ##Show this help message.
top/x300/Makefile.x300.inc
+9 -19
View File
@@ -39,23 +39,15 @@ include $(LIB_DIR)/rfnoc/Makefile.srcs
include $(LIB_DIR)/axi4s_sv/Makefile.srcs
include $(LIB_DIR)/rfnoc/xport_sv/Makefile.srcs
# For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and
# DUC, Replay, and of course the radio. Any other block needs to use the
# RFNOC_OOT_MAKEFILE_SRCS variable (see below).
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs
# If out-of-tree modules want to be compiled into this image, then they need to
# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
# source files.
-include $(RFNOC_OOT_MAKEFILE_SRCS)
IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
EDGE_FILE ?= $(DEFAULT_EDGE_FILE)
ifdef ARTIFACT_DIR
include $(ARTIFACT_DIR)/Makefile.inc
endif
##################################################
# Sources
@@ -73,8 +65,7 @@ capture_ddrlvds.v \
gen_ddrlvds.v \
bus_int.v \
x300.xdc \
timing.xdc \
$(IMAGE_CORE)
timing.xdc
ifdef BUILD_10G
SFP_SERDES_SRCS += $(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(abspath x300_10ge.xdc) $(TEN_GIGE_PHY_SRCS) $(IP_TEN_GIGE_PHY_XCI_SRCS)
@@ -112,21 +103,20 @@ $(PACKET_PROC_SRCS) $(DSP_SRCS) $(DRAM_SRCS) \
$(AXI_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
$(RFNOC_SRCS) $(LIB_IP_XCI_SRCS) \
$(RFNOC_FRAMEWORK_SRCS) \
$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) $(RFNOC_BLOCK_RADIO_SRCS) \
$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
$(RFNOC_BLOCK_REPLAY_SRCS) \
$(RFNOC_OOT_SRCS) \
$(AXI4S_SV_SRCS) $(RFNOC_XPORT_SV_SRCS) \
$(RFNOC_IMAGE_CORE_SRCS)
EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(DEFAULT_RFNOC_IMAGE_CORE_FILE:.v=.vh)"
# Pass the image core header files required by RFNoC
# to Vivado as Verilog definitions.
IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(ARTIFACT_DIR)/rfnoc_image_core.vh"
##################################################
# Dependency Targets
##################################################
.SECONDEXPANSION:
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF)
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS)
# DESIGN_SRCS and VERILOG_DEFS must be defined
bin: .prereqs
top/x300/x300_HG_rfnoc_image_core.yml
+72
View File
@@ -0,0 +1,72 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'x310'
image_core_name: 'usrp_x300_fpga_HG' # This is used for the bitfile, DTS, and report
default_target: 'X300_HG'
inherit:
- 'yaml_include/x3xx_radio_base.yml'
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
buff_size: 32768 # Ingress buffer size for data
ep1:
buff_size: 0
ep2:
buff_size: 32768
ep3:
buff_size: 0
ep4:
buff_size: 4096
ctrl: False
data: True
ep5:
buff_size: 4096
ctrl: False
data: True
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
replay0:
block_desc: 'replay.yml'
parameters:
NUM_PORTS: 2
MEM_DATA_W: 64
MEM_ADDR_W: 30
priority: 99 # Make sure they come after the blocks defined in x3xx_radio_base.yml
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# Replay Connections
- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
#
# BSP Connections
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect (Always "_device"_)
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
top/x300/x300_XG_rfnoc_image_core.yml
+72
View File
@@ -0,0 +1,72 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'x310'
image_core_name: 'usrp_x300_fpga_XG' # This is used for the bitfile, DTS, and report
default_target: 'X300_XG'
inherit:
- 'yaml_include/x3xx_radio_base.yml'
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
buff_size: 32768 # Ingress buffer size for data
ep1:
buff_size: 0
ep2:
buff_size: 32768
ep3:
buff_size: 0
ep4:
buff_size: 4096
ctrl: False
data: True
ep5:
buff_size: 4096
ctrl: False
data: True
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
replay0:
block_desc: 'replay.yml'
parameters:
NUM_PORTS: 2
MEM_DATA_W: 64
MEM_ADDR_W: 30
priority: 99 # Make sure they come after the blocks defined in x3xx_radio_base.yml
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# Replay Connections
- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
#
# BSP Connections
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect (Always "_device"_)
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
top/x300/x300_rfnoc_image_core.v
-1501
View File
File diff suppressed because it is too large Load Diff
top/x300/x300_rfnoc_image_core.vh
-19
View File
@@ -1,19 +0,0 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for x300)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: x300_rfnoc_image_core.yml
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/x300/x300_rfnoc_image_core.yml
-131
View File
@@ -1,131 +0,0 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'x300'
default_target: 'X300_HG'
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size: 32768 # Ingress buffer size for data
ep1:
ctrl: False
data: True
buff_size: 0
ep2:
ctrl: False
data: True
buff_size: 32768
ep3:
ctrl: False
data: True
buff_size: 0
ep4:
ctrl: False
data: True
buff_size: 4096
ep5:
ctrl: False
data: True
buff_size: 4096
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
duc0: # NoC block name
block_desc: 'duc.yml' # Block device descriptor file
parameters:
NUM_PORTS: 1
ddc0:
block_desc: 'ddc.yml'
parameters:
NUM_PORTS: 2
radio0:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
duc1:
block_desc: 'duc.yml'
parameters:
NUM_PORTS: 1
ddc1:
block_desc: 'ddc.yml'
parameters:
NUM_PORTS: 2
radio1:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
replay0:
block_desc: 'replay.yml'
parameters:
NUM_PORTS: 2
MEM_ADDR_W: 30
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# RF A TX
- { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 }
- { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
# RF A RX
- { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
- { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
# RF A RX2
- { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
- { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
#
# RF B TX
- { srcblk: ep2, srcport: out0, dstblk: duc1, dstport: in_0 }
- { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 }
# RF B RX
- { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 }
- { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 }
# RF B RX2
- { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
- { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 }
#
# Replay Connections
- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
#
# BSP Connections
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect (Always "_device"_)
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
top/x300/x300_static_router.hex
-17
View File
@@ -1,17 +0,0 @@
00000010
004001c0
01c00240
02400200
02000040
02410201
02010080
00c00280
02800300
030002c0
02c000c0
030102c1
02c10100
01400340
03400140
01800341
03410180
top/x300/x310_HG_rfnoc_image_core.yml
+72
View File
@@ -0,0 +1,72 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'x310'
image_core_name: 'usrp_x310_fpga_HG' # This is used for the bitfile, DTS, and report
default_target: 'X310_HG'
inherit:
- 'yaml_include/x3xx_radio_base.yml'
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
buff_size: 65536 # Ingress buffer size for data
ep1:
buff_size: 0
ep2:
buff_size: 65536
ep3:
buff_size: 0
ep4:
buff_size: 4096
ctrl: False
data: True
ep5:
buff_size: 4096
ctrl: False
data: True
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
replay0:
block_desc: 'replay.yml'
parameters:
NUM_PORTS: 2
MEM_DATA_W: 64
MEM_ADDR_W: 30
priority: 99 # Make sure they come after the blocks defined in x3xx_radio_base.yml
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# Replay Connections
- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
#
# BSP Connections
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect (Always "_device"_)
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
top/x300/x310_XG_rfnoc_image_core.yml
+72
View File
@@ -0,0 +1,72 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'x310'
image_core_name: 'usrp_x310_fpga_XG' # This is used for the bitfile, DTS, and report
default_target: 'X310_XG'
inherit:
- 'yaml_include/x3xx_radio_base.yml'
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
buff_size: 65536 # Ingress buffer size for data
ep1:
buff_size: 0
ep2:
buff_size: 65536
ep3:
buff_size: 0
ep4:
buff_size: 4096
ctrl: False
data: True
ep5:
buff_size: 4096
ctrl: False
data: True
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
replay0:
block_desc: 'replay.yml'
parameters:
NUM_PORTS: 2
MEM_DATA_W: 64
MEM_ADDR_W: 30
priority: 99 # Make sure they come after the blocks defined in x3xx_radio_base.yml
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# Replay Connections
- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
#
# BSP Connections
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect (Always "_device"_)
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
top/x300/x310_rfnoc_image_core.v
-1501
View File
File diff suppressed because it is too large Load Diff
top/x300/x310_rfnoc_image_core.vh
-19
View File
@@ -1,19 +0,0 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for x310)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: x310_rfnoc_image_core.yml
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/x300/x310_static_router.hex
-17
View File
@@ -1,17 +0,0 @@
00000010
004001c0
01c00240
02400200
02000040
02410201
02010080
00c00280
02800300
030002c0
02c000c0
030102c1
02c10100
01400340
03400140
01800341
03410180
top/x300/x310_rfnoc_image_core.yml → top/x300/yaml_include/x3xx_radio_base.yml
+3 -26
View File
@@ -7,8 +7,6 @@ license: >- # License information used in file heade
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'x310'
default_target: 'X310_HG'
# A list of all stream endpoints in design
# ----------------------------------------
@@ -16,7 +14,7 @@ stream_endpoints:
ep0: # Stream endpoint name
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size: 65536 # Ingress buffer size for data
buff_size: 32768 # Ingress buffer size for data
ep1:
ctrl: False
data: True
@@ -24,19 +22,11 @@ stream_endpoints:
ep2:
ctrl: False
data: True
buff_size: 65536
buff_size: 32768
ep3:
ctrl: False
data: True
buff_size: 0
ep4:
ctrl: False
data: True
buff_size: 4096
ep5:
ctrl: False
data: True
buff_size: 4096
# A list of all NoC blocks in design
# ----------------------------------
@@ -65,12 +55,6 @@ noc_blocks:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
replay0:
block_desc: 'replay.yml'
parameters:
NUM_PORTS: 2
MEM_DATA_W: 64
MEM_ADDR_W: 30
# A list of all static connections in design
# ------------------------------------------
@@ -100,16 +84,9 @@ connections:
- { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
- { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 }
#
# Replay Connections
- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
#
# BSP Connections
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
@@ -129,4 +106,4 @@ clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
top/x400/Makefile
+31 -197
View File
@@ -22,84 +22,24 @@ BUILD_BASE_DIR ?= .
# Base directory for the build outputs.
BUILD_OUTPUT_DIR ?= $(BUILD_BASE_DIR)/build
# Definitions
# MGT Types from x4xx_mgt_type.vh
MGT_100GbE = 5
MGT_Aurora = 3
MGT_10GbE = 2
MGT_Disabled = 0
# For a 4-lane MGT like 100GBE set QSFPx_0=MGT_100GbE and all others to
# MGT_Disabled. For a 1-lane MGT like 10GbE do not set anything for unused
# lanes. This ensures something is defined only for the lanes that are used, so
# that the TX/RX signals are connected. The presence of a define causes TX/RX
# to be declared, whereas declaring TX/RX on an unused lane will cause an error
# in bitgen for unconstrained pins after it is optimized out.
QSFP0_10GBE = QSFP0_0=$(MGT_10GbE)
QSFP0_4X10GBE = QSFP0_0=$(MGT_10GbE) QSFP0_1=$(MGT_10GbE) QSFP0_2=$(MGT_10GbE) QSFP0_3=$(MGT_10GbE)
QSFP0_100GBE = QSFP0_0=$(MGT_100GbE) QSFP0_1=$(MGT_Disabled) QSFP0_2=$(MGT_Disabled) QSFP0_3=$(MGT_Disabled)
QSFP1_10GBE = QSFP1_0=$(MGT_10GbE)
QSFP1_4X10GBE = QSFP1_0=$(MGT_10GbE) QSFP1_1=$(MGT_10GbE) QSFP1_2=$(MGT_10GbE) QSFP1_3=$(MGT_10GbE)
QSFP1_100GBE = QSFP1_0=$(MGT_100GbE) QSFP1_1=$(MGT_Disabled) QSFP1_2=$(MGT_Disabled) QSFP1_3=$(MGT_Disabled)
# Target specific variables
X410_IP: DEFS += $(QSFP0_10GBE) RF_BW=100
X410_X1_100: DEFS += $(QSFP0_10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_XG_100: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_X4_100: DEFS += $(QSFP0_4X10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_X4C_100: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=0 DRAM_CH=0
X410_C1_100: DEFS += $(QSFP0_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_UC_100: DEFS += $(QSFP1_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_C1_200: DEFS += $(QSFP0_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_UC_200: DEFS += $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_CG_200: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_X1_200: DEFS += $(QSFP0_10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_XG_200: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_X4_200: DEFS += $(QSFP0_4X10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_X4C_200: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=0 DRAM_CH=0
X410_X1_400: DEFS += $(QSFP0_10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_BANKS=2 DRAM_CH=4*$(DRAM) DRAM_W=128
X410_XG_400: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_BANKS=2 DRAM_CH=4*$(DRAM) DRAM_W=128
X410_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_BANKS=2 DRAM_CH=4*$(DRAM) DRAM_W=128
X410_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_BANKS=0 DRAM_CH=0
X410_UC_400: DEFS += $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_BANKS=0 DRAM_CH=0
X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_BANKS=0 DRAM_CH=0
X440_X4_200: DEFS += $(QSFP0_4X10GBE) RF_BW=200 RF_CORE_FULL=1 DRAM_BANKS=0 DRAM_CH=0
X440_X1_400: DEFS += $(QSFP0_10GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_BANKS=2 DRAM_CH=8*$(DRAM) DRAM_W=128
X440_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_BANKS=2 DRAM_CH=8*$(DRAM) DRAM_W=128
X440_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_BANKS=0 DRAM_CH=0
X440_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_BANKS=0 DRAM_CH=0
X440_X1_1600: DEFS += $(QSFP0_10GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_BANKS=2 DRAM_CH=2*$(DRAM) DRAM_W=512
X440_X4_1600: DEFS += $(QSFP0_4X10GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_BANKS=2 DRAM_CH=2*$(DRAM) DRAM_W=512
X440_C1_1600: DEFS += $(QSFP0_100GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_BANKS=0 DRAM_CH=0
X440_CG_1600: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_BANKS=0 DRAM_CH=0
# Sane defaults for IP builds
X410_IP: DEFS += QSFP0_0=2 RF_BW=100
X440_IP: DEFS += QSFP0_0=2 RF_BW=400
# DRAM IP inclusion. Set to 1 to include DRAM memory controller in design, 0 to
# exclude it. Note that some targets exclude it regardless of this setting.
DRAM ?= 1
IMAGE_CORE_NAME ?= usrp_fpga
DEFS += $(OPTIONS)
# Initialize a build seed. This can be changed to randomly affect build results.
BUILD_SEED ?= 0
DEFS += BUILD_SEED=$(BUILD_SEED)
# Default value for incremental Vivado build is disabled.
# Default value for incremental Vivado build is disabled.
INCR_BUILD ?= 0
# Defaults specific to the various targets:
X410_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_200_static_router.hex)
X410_X4C_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_x4c_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_x4c_200_static_router.hex)
X410_CG_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_cg_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_cg_200_static_router.hex)
X410_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex)
X410_400_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_d_static_router.hex)
X440_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_200_static_router.hex)
X440_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_400_static_router.hex)
X440_400_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_400_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_400_d_static_router.hex)
X440_1600_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_1600_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_1600_static_router.hex)
X440_1600_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_1600_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_1600_d_static_router.hex)
# Option to stop after RTL elaboration. Use this flag as a synthesis check.
ifndef TARGET
ifeq ($(CHECK), 1)
@@ -114,25 +54,31 @@ ifndef TARGET
endif
TOP ?= x4xx
# vivado_build($1=Device, $2=Definitions, $3=Defaults)
vivado_build = make -f Makefile.x4xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3 INCR_BUILD=$(INCR_BUILD)
vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3
ifdef ARTIFACT_DIR
BUILD_DIR = $(ARTIFACT_DIR)
endif
# vivado_build($1=Device, $2=Option)
# vivado_build($1=Device (X410 or X440), $2=Definitions)
vivado_build = make -f Makefile.x4xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) EXTRA_DEFS="$2" TOP_MODULE=$(TOP) $2 INCR_BUILD=$(INCR_BUILD)
vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) EXTRA_DEFS="$2" TOP_MODULE=$(TOP) $2
# vivado_build($1=Device)
ifeq ($(TARGET),bin)
post_build = @\
mkdir -p $(BUILD_OUTPUT_DIR); \
echo "Exporting bitstream file..."; \
cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/x4xx.bit $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
cp $(ARTIFACT_DIR)/x4xx.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
echo "Exporting build report..."; \
cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
echo "Build DONE ... $(1)_$(2)";
cp $(ARTIFACT_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
echo "Build DONE ... $(IMAGE_CORE_NAME)";
else
post_build = @echo "Skipping bitfile export."
endif
##
##Available Targets
##-------------|-----------|----|-----------------|-----------------|------------
##Target | Bandwidth | Ch | QSFP0 | QSFP1 | DRAM
##-------------|-----------|----|-----------------|-----------------|------------
@@ -165,124 +111,13 @@ endif
##* Note: Not all targets are shipped with UHD
##* Note: Some YAML configurations might not use all available DRAM channels.
X410_X1_100: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X1_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,X1_100)
X410: X410_IP build/$(IMAGE_CORE_NAME).dts
$(call vivado_build,X410,$(DEFS) X410=1)
$(call post_build,X410)
X440: X440_IP build/$(IMAGE_CORE_NAME).dts
$(call vivado_build,X440,$(DEFS) X440=1)
$(call post_build,X440)
X410_XG_100: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_XG_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,XG_100)
X410_X4_100: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X4_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,X4_100)
X410_X4C_100: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X4C_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_X4C_200_DEFAULTS))
$(call post_build,X410,X4C_100)
X410_C1_100: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_C1_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
$(call post_build,X410,C1_100)
X410_UC_100: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_UC_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
$(call post_build,X410,UC_100)
X410_X1_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X1_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,X1_200)
X410_XG_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_XG_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,XG_200)
X410_X4_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X4_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,X4_200)
X410_X4C_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X4C_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_X4C_200_DEFAULTS))
$(call post_build,X410,X4C_200)
X410_C1_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_C1_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
$(call post_build,X410,C1_200)
X410_UC_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_UC_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
$(call post_build,X410,UC_200)
X410_X1_400: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X1_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS))
$(call post_build,X410,X1_400)
X410_XG_400: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_XG_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS))
$(call post_build,X410,XG_400)
X410_X4_400: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X4_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS))
$(call post_build,X410,X4_400)
X410_C1_400: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_C1_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
$(call post_build,X410,C1_400)
X410_UC_400: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_UC_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
$(call post_build,X410,UC_400)
X410_CG_400: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_CG_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
$(call post_build,X410,CG_400)
X440_X4_200: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_X4_200.dts
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_200_DEFAULTS))
$(call post_build,X440,X4_200)
X440_X1_400: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_X1_400.dts
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_D_DEFAULTS))
$(call post_build,X440,X1_400)
X440_X4_400: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_X4_400.dts
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_D_DEFAULTS))
$(call post_build,X440,X4_400)
X440_C1_400: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_C1_400.dts
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_DEFAULTS))
$(call post_build,X440,C1_400)
X440_CG_400: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_CG_400.dts
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_DEFAULTS))
$(call post_build,X440,CG_400)
X440_X1_1600: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_X1_1600.dts
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_D_DEFAULTS))
$(call post_build,X440,X1_1600)
X440_X4_1600: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_X4_1600.dts
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_D_DEFAULTS))
$(call post_build,X440,X4_1600)
X440_C1_1600: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_C1_1600.dts
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_DEFAULTS))
$(call post_build,X440,C1_1600)
X440_CG_1600: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_CG_1600.dts
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_DEFAULTS))
$(call post_build,X440,CG_1600)
##
##Experimental Targets
##-------------|-----------|----|-----------------|-----------------|------------
##Target | Bandwidth | Ch | QSFP0 | QSFP1 | DRAM
##-------------|-----------|----|-----------------|-----------------|------------
##X410_CG_200 | 200 | 4 | 100 GbE | 100 GbE | 64b x 4 Ch
X410_CG_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_CG_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
$(call post_build,X410,CG_200)
##
##Other Make Targets
@@ -290,12 +125,12 @@ X410_CG_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_CG_200.dts
.DEFAULT_GOAL := all
all: X410_X4_200 X410_CG_400 X410_UC_200 X440_X4_200 X440_X4_400 X440_CG_400 X440_X4_1600 X440_CG_1600 ##(Default targets)
all: X410_IP
X410_IP: ##Build IP only.
X410_IP: ##Build X410 IP only.
+$(call vivado_ip,X410,$(DEFS) X410=1)
X440_IP: ##Build IP only.
X440_IP: ##Build X440 IP only.
+$(call vivado_ip,X440,$(DEFS) X440=1)
$(BUILD_OUTPUT_DIR)/usrp_x410%.dts: dts/*.dts dts/*.dtsi
@@ -305,7 +140,7 @@ $(BUILD_OUTPUT_DIR)/usrp_x410%.dts: dts/*.dts dts/*.dtsi
--output dts/x410-version-info.dtsi \
--components fpga,cpld_ifc,db_gpio_ifc,rf_core_100m,rf_core_400m
${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \
$$(python3 tools/get_dts_input.py --target $@)
$(ARTIFACT_DIR)/device_tree.dts
$(BUILD_OUTPUT_DIR)/usrp_x440%.dts: dts/*.dts dts/*.dtsi
-mkdir -p $(BUILD_OUTPUT_DIR)
@@ -314,17 +149,17 @@ $(BUILD_OUTPUT_DIR)/usrp_x440%.dts: dts/*.dts dts/*.dtsi
--output dts/x440-version-info.dtsi \
--components fpga,cpld_ifc,db_gpio_ifc,rf_core_full
${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \
$$(python3 tools/get_dts_input.py --target $@)
$(ARTIFACT_DIR)/device_tree.dts
clean: ##Clean up all target build outputs.
@echo "Cleaning targets..."
@rm -rf $(BUILD_BASE_DIR)/build-X4*
@rm -rf $(BUILD_BASE_DIR)/build-X* $(BUILD_BASE_DIR)/build-x*
@rm -rf $(BUILD_OUTPUT_DIR)
cleanall: ##Clean up all target and IP build outputs.
@echo "Cleaning targets and IP..."
@rm -rf build-ip
@rm -rf $(BUILD_BASE_DIR)/build-X4*
@rm -rf $(BUILD_BASE_DIR)/build-*
@rm -rf $(BUILD_OUTPUT_DIR)
help: ##Show this help message.
@@ -334,7 +169,6 @@ help: ##Show this help message.
##Supported Options
##-----------------
##INCR_BUILD=0 Use incremental Vivado build to speed up consecutive runs
##DRAM=0 Exclude DDR4 memory controller IP from the FPGA build.
##GUI=1 Launch the build in the Vivado GUI.
##PROJECT=1 Save Vivado project file, otherwise it's created in memory.
##CHECK=1 Launch the syntax checker instead of building a bitfile.
top/x400/Makefile.x4xx.inc
+12 -62
View File
@@ -41,24 +41,15 @@ include $(LIB_DIR)/axi4s_sv/Makefile.srcs
include $(LIB_DIR)/axi4lite_sv/Makefile.srcs
include $(LIB_DIR)/rfnoc/xport_sv/Makefile.srcs
# For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and
# DUC, Replay, and of course the radio. Any other block needs to use the
# RFNOC_OOT_MAKEFILE_SRCS variable (see below).
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_null_src_sink/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs
# If out-of-tree modules want to be compiled into this image, then they need to
# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
# source files.
-include $(RFNOC_OOT_MAKEFILE_SRCS)
IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
EDGE_FILE ?= $(DEFAULT_EDGE_FILE)
ifdef ARTIFACT_DIR
include $(ARTIFACT_DIR)/Makefile.inc
endif
##################################################
# Sources
@@ -86,8 +77,7 @@ x4xx_pps_sync.v \
dboards/ctrlport_byte_serializer.v \
dboards/ctrlport_clk_crossing_derived.v \
dboards/db_gpio_reordering.v \
ipass_present_controller.v \
$(IMAGE_CORE)
ipass_present_controller.v
ifdef X410
TOP_SRCS += \
@@ -151,44 +141,7 @@ constraints/pins/x440/db_gpio.xdc \
constraints/timing/x440.xdc
endif
# Definitions
# MGT Types from x4xx_mgt_type.vh
MGT_100GbE = 5
MGT_Aurora = 3
MGT_10GbE = 2
MGT_Disabled = 0
# Check if any of the ports are set to 10Gbe
ifneq (,$(findstring =$(MGT_10GbE),$(EXTRA_DEFS)))
MB_XDC += constraints/timing/qsfp_10gbe.xdc
endif
# Add pin constraints for QSFP pins
ifneq (,$(findstring QSFP0_0,"$(EXTRA_DEFS)"))
MB_XDC += constraints/pins/qsfp0_0.xdc
endif
ifneq (,$(findstring QSFP0_1,$(EXTRA_DEFS)))
MB_XDC += constraints/pins/qsfp0_1.xdc
endif
ifneq (,$(findstring QSFP0_2,$(EXTRA_DEFS)))
MB_XDC += constraints/pins/qsfp0_2.xdc
endif
ifneq (,$(findstring QSFP0_3,$(EXTRA_DEFS)))
MB_XDC += constraints/pins/qsfp0_3.xdc
endif
ifneq (,$(findstring QSFP1_0,$(EXTRA_DEFS)))
MB_XDC += constraints/pins/qsfp1_0.xdc
endif
ifneq (,$(findstring QSFP1_1,$(EXTRA_DEFS)))
MB_XDC += constraints/pins/qsfp1_1.xdc
endif
ifneq (,$(findstring QSFP1_2,$(EXTRA_DEFS)))
MB_XDC += constraints/pins/qsfp1_2.xdc
endif
ifneq (,$(findstring QSFP1_3,$(EXTRA_DEFS)))
MB_XDC += constraints/pins/qsfp1_3.xdc
endif
MB_XDC += $(RFNOC_XDC_SRCS)
DESIGN_SRCS = $(abspath $(MB_XDC))
@@ -205,30 +158,27 @@ $(XGE_PCS_PMA_SRCS) \
$(PACKET_PROC_SRCS) $(VITA_SRCS) $(DSP_SRCS) $(DRAM_SRCS) \
$(RADIO_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
$(RFNOC_SRCS) $(RFNOC_OOT_SRCS) $(LIB_IP_XCI_SRCS) $(LIB_HLS_IP_SRCS) $(LIBCOREGEN_SRCS) \
$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) \
$(RFNOC_BLOCK_RADIO_SRCS) $(RFNOC_BLOCK_NULL_SRC_SINK_SRCS) \
$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
$(RFNOC_BLOCK_REPLAY_SRCS) \
$(DB_COMMON_SRCS) $(WHITE_RABBIT_SRCS) $(RFNOC_FRAMEWORK_SRCS) \
$(DB_COMMON_SRCS) $(RFNOC_FRAMEWORK_SRCS) \
$(WB_SPI_SRCS) $(RFNOC_XPORT_SV_SRCS) \
$(RFNOC_IMAGE_CORE_SRCS) \
)
# Pass the edge table and image core header files required by RFNoC
# Pass the image core header files required by RFNoC
# to Vivado as Verilog definitions.
EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(ARTIFACT_DIR)/rfnoc_image_core.vh"
##################################################
# Dependency Targets
##################################################
.SECONDEXPANSION:
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF)
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS)
# DESIGN_SRCS and VERILOG_DEFS must be defined
bin: .prereqs
@echo "Build directory:: $(BUILD_DIR)"
@echo "Printing MB_XDC:: $(MB_XDC)"
@echo "Printing EXTRA_DEFS:: $(EXTRA_DEFS)"
@echo "Printing EXTRA_DEFS:: $(EXTRA_DEFS) $(RFNOC_IMAGE_CORE_DEFS)"
$(call BUILD_VIVADO_DESIGN,$(abspath ./build_x4xx.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
synth: .prereqs
top/x400/x410_200_rfnoc_image_core.v
-1781
View File
File diff suppressed because it is too large Load Diff
top/x400/x410_200_rfnoc_image_core.vh
-19
View File
@@ -1,19 +0,0 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for x410)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: x410_200_rfnoc_image_core.yml
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/x400/x410_200_static_router.hex
-25
View File
@@ -1,25 +0,0 @@
00000018
00400240
024002c0
02c00280
02800040
00800241
024102c1
02c10281
02810080
00c00300
03000380
03800340
034000c0
01000301
03010381
03810341
03410100
014003c0
03c00140
018003c1
03c10180
01c003c2
03c201c0
020003c3
03c30200
top/x400/x410_400_d_rfnoc_image_core.v
-1729
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File diff suppressed because it is too large Load Diff
top/x400/x410_400_d_rfnoc_image_core.vh
-19
View File
@@ -1,19 +0,0 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for x410)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: x410_400_d_rfnoc_image_core.yml
//
`define CHDR_WIDTH 128
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/x400/x410_400_d_rfnoc_image_core.yml
-139
View File
@@ -1,139 +0,0 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 128 # Bit width of the CHDR bus for this image
device: 'x410' # USRP type
image_core_name: 'x410_400_d' # Name to use for the RFNoC Image Core files
default_target: 'X410_X4_400' # Default make target
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size_bytes: 32768 # Stream endpoint buffer size
ep1:
ctrl: False
data: True
buff_size_bytes: 32768
ep2:
ctrl: False
data: True
buff_size_bytes: 32768
ep3:
ctrl: False
data: True
buff_size_bytes: 32768
ep4:
ctrl: False
data: True
buff_size_bytes: 32768
ep5:
ctrl: False
data: True
buff_size_bytes: 32768
ep6:
ctrl: False
data: True
buff_size_bytes: 32768
ep7:
ctrl: False
data: True
buff_size_bytes: 32768
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
radio0:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl # The clock that is used for the control
# interface. This is the default clock,
# so we could skip it.
timebase_clock: _device_.radio # The clock that is used for the timebase.
radio1:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl
timebase_clock: _device_.radio
replay0:
block_desc: 'replay.yml'
parameters:
NUM_PORTS: 2
MEM_DATA_W: 128
MEM_ADDR_W: 32
replay1:
block_desc: 'replay.yml'
parameters:
NUM_PORTS: 2
MEM_DATA_W: 128
MEM_ADDR_W: 32
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# RF A:0 TX
- { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
# RF A:0 RX
- { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
# RF A:1 TX
- { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 }
# RF A:1 RX
- { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 }
#
# RF B:0 TX
- { srcblk: ep2, srcport: out0, dstblk: radio1, dstport: in_0 }
# RF B:0 RX
- { srcblk: radio1, srcport: out_0, dstblk: ep2, dstport: in0 }
# RF B:1 TX
- { srcblk: ep3, srcport: out0, dstblk: radio1, dstport: in_1 }
# RF B:1 RX
- { srcblk: radio1, srcport: out_1, dstblk: ep3, dstport: in0 }
#
# Replay Connections
- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
- { srcblk: ep6, srcport: out0, dstblk: replay1, dstport: in_0 }
- { srcblk: replay1, srcport: out_0, dstblk: ep6, dstport: in0 }
- { srcblk: ep7, srcport: out0, dstblk: replay1, dstport: in_1 }
- { srcblk: replay1, srcport: out_1, dstblk: ep7, dstport: in0 }
#
# BSP Connections
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 }
- { srcblk: replay1, srcport: axi_ram, dstblk: _device_, dstport: dram1 }
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect (Always "_device_")
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
- { srcblk: _device_, srcport: dram, dstblk: replay1, dstport: mem }
top/x400/x410_400_d_static_router.hex
-17
View File
@@ -1,17 +0,0 @@
00000010
00400240
02400040
00800241
02410080
00c00280
028000c0
01000281
02810100
014002c0
02c00140
018002c1
02c10180
01c00300
030001c0
02000301
03010200
top/x400/x410_400_rfnoc_image_core.v
-985
View File
@@ -1,985 +0,0 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rfnoc_image_core (for x410)
//
// Description:
//
// The RFNoC Image Core contains the Verilog description of the RFNoC design
// to be loaded onto the FPGA.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: x410_400_rfnoc_image_core.yml
//
`default_nettype none
module rfnoc_image_core #(
parameter [31:0] CHDR_W = 512,
parameter [31:0] PORT_W = 512,
parameter [31:0] ETH0_W = 64,
parameter [31:0] ETH1_W = 64,
parameter [31:0] ETH2_W = 64,
parameter [31:0] ETH3_W = 64,
parameter [31:0] ETH4_W = 64,
parameter [31:0] DMA_W = 64,
parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1
) (
// Clocks
input wire chdr_aclk,
input wire ctrl_aclk,
input wire core_arst,
input wire ce_clk,
input wire radio_clk,
input wire radio_2x_clk,
input wire dram_clk,
// Basic
input wire [ 15:0] device_id,
// IO ports /////////////////////////
// ctrlport_radio0
output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 31:0] m_ctrlport_radio0_resp_data,
// ctrlport_radio1
output wire [ 0:0] m_ctrlport_radio1_req_wr,
output wire [ 0:0] m_ctrlport_radio1_req_rd,
output wire [ 19:0] m_ctrlport_radio1_req_addr,
output wire [ 31:0] m_ctrlport_radio1_req_data,
output wire [ 3:0] m_ctrlport_radio1_req_byte_en,
output wire [ 0:0] m_ctrlport_radio1_req_has_time,
output wire [ 63:0] m_ctrlport_radio1_req_time,
input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 31:0] m_ctrlport_radio1_resp_data,
// time
input wire [ 63:0] radio_time,
// radio0
input wire [1023:0] radio_rx_data_radio0,
input wire [ 31:0] radio_rx_stb_radio0,
output wire [ 31:0] radio_rx_running_radio0,
output wire [1023:0] radio_tx_data_radio0,
input wire [ 31:0] radio_tx_stb_radio0,
output wire [ 31:0] radio_tx_running_radio0,
// radio1
input wire [1023:0] radio_rx_data_radio1,
input wire [ 31:0] radio_rx_stb_radio1,
output wire [ 31:0] radio_rx_running_radio1,
output wire [1023:0] radio_tx_data_radio1,
input wire [ 31:0] radio_tx_stb_radio1,
output wire [ 31:0] radio_tx_running_radio1,
// dram0
input wire [ 0:0] dram0_axi_rst,
output wire [ 7:0] dram0_m_axi_awid,
output wire [ 383:0] dram0_m_axi_awaddr,
output wire [ 63:0] dram0_m_axi_awlen,
output wire [ 23:0] dram0_m_axi_awsize,
output wire [ 15:0] dram0_m_axi_awburst,
output wire [ 7:0] dram0_m_axi_awlock,
output wire [ 31:0] dram0_m_axi_awcache,
output wire [ 23:0] dram0_m_axi_awprot,
output wire [ 31:0] dram0_m_axi_awqos,
output wire [ 31:0] dram0_m_axi_awregion,
output wire [ 7:0] dram0_m_axi_awuser,
output wire [ 7:0] dram0_m_axi_awvalid,
input wire [ 7:0] dram0_m_axi_awready,
output wire [4191:0] dram0_m_axi_wdata,
output wire [ 511:0] dram0_m_axi_wstrb,
output wire [ 7:0] dram0_m_axi_wlast,
output wire [ 7:0] dram0_m_axi_wuser,
output wire [ 7:0] dram0_m_axi_wvalid,
input wire [ 7:0] dram0_m_axi_wready,
input wire [ 7:0] dram0_m_axi_bid,
input wire [ 15:0] dram0_m_axi_bresp,
input wire [ 7:0] dram0_m_axi_buser,
input wire [ 7:0] dram0_m_axi_bvalid,
output wire [ 7:0] dram0_m_axi_bready,
output wire [ 7:0] dram0_m_axi_arid,
output wire [ 383:0] dram0_m_axi_araddr,
output wire [ 63:0] dram0_m_axi_arlen,
output wire [ 23:0] dram0_m_axi_arsize,
output wire [ 15:0] dram0_m_axi_arburst,
output wire [ 7:0] dram0_m_axi_arlock,
output wire [ 31:0] dram0_m_axi_arcache,
output wire [ 31:0] dram0_m_axi_arprot,
output wire [ 31:0] dram0_m_axi_arqos,
output wire [ 31:0] dram0_m_axi_arregion,
output wire [ 7:0] dram0_m_axi_aruser,
output wire [ 7:0] dram0_m_axi_arvalid,
input wire [ 7:0] dram0_m_axi_arready,
input wire [ 7:0] dram0_m_axi_rid,
input wire [4191:0] dram0_m_axi_rdata,
input wire [ 15:0] dram0_m_axi_rresp,
input wire [ 7:0] dram0_m_axi_rlast,
input wire [ 7:0] dram0_m_axi_ruser,
input wire [ 7:0] dram0_m_axi_rvalid,
output wire [ 7:0] dram0_m_axi_rready,
// dram1
input wire [ 0:0] dram1_axi_rst,
output wire [ 7:0] dram1_m_axi_awid,
output wire [ 383:0] dram1_m_axi_awaddr,
output wire [ 63:0] dram1_m_axi_awlen,
output wire [ 23:0] dram1_m_axi_awsize,
output wire [ 15:0] dram1_m_axi_awburst,
output wire [ 7:0] dram1_m_axi_awlock,
output wire [ 31:0] dram1_m_axi_awcache,
output wire [ 23:0] dram1_m_axi_awprot,
output wire [ 31:0] dram1_m_axi_awqos,
output wire [ 31:0] dram1_m_axi_awregion,
output wire [ 7:0] dram1_m_axi_awuser,
output wire [ 7:0] dram1_m_axi_awvalid,
input wire [ 7:0] dram1_m_axi_awready,
output wire [4191:0] dram1_m_axi_wdata,
output wire [ 511:0] dram1_m_axi_wstrb,
output wire [ 7:0] dram1_m_axi_wlast,
output wire [ 7:0] dram1_m_axi_wuser,
output wire [ 7:0] dram1_m_axi_wvalid,
input wire [ 7:0] dram1_m_axi_wready,
input wire [ 7:0] dram1_m_axi_bid,
input wire [ 15:0] dram1_m_axi_bresp,
input wire [ 7:0] dram1_m_axi_buser,
input wire [ 7:0] dram1_m_axi_bvalid,
output wire [ 7:0] dram1_m_axi_bready,
output wire [ 7:0] dram1_m_axi_arid,
output wire [ 383:0] dram1_m_axi_araddr,
output wire [ 63:0] dram1_m_axi_arlen,
output wire [ 23:0] dram1_m_axi_arsize,
output wire [ 15:0] dram1_m_axi_arburst,
output wire [ 7:0] dram1_m_axi_arlock,
output wire [ 31:0] dram1_m_axi_arcache,
output wire [ 31:0] dram1_m_axi_arprot,
output wire [ 31:0] dram1_m_axi_arqos,
output wire [ 31:0] dram1_m_axi_arregion,
output wire [ 7:0] dram1_m_axi_aruser,
output wire [ 7:0] dram1_m_axi_arvalid,
input wire [ 7:0] dram1_m_axi_arready,
input wire [ 7:0] dram1_m_axi_rid,
input wire [4191:0] dram1_m_axi_rdata,
input wire [ 15:0] dram1_m_axi_rresp,
input wire [ 7:0] dram1_m_axi_rlast,
input wire [ 7:0] dram1_m_axi_ruser,
input wire [ 7:0] dram1_m_axi_rvalid,
output wire [ 7:0] dram1_m_axi_rready,
// Transport Adapters ///////////////
// Transport 0 (eth0)
input wire [PORT_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast,
input wire s_eth0_tvalid,
output wire s_eth0_tready,
output wire [PORT_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast,
output wire m_eth0_tvalid,
input wire m_eth0_tready,
// Transport 1 (eth1)
input wire [PORT_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast,
input wire s_eth1_tvalid,
output wire s_eth1_tready,
output wire [PORT_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast,
output wire m_eth1_tvalid,
input wire m_eth1_tready,
// Transport 2 (eth2)
input wire [PORT_W-1:0] s_eth2_tdata,
input wire s_eth2_tlast,
input wire s_eth2_tvalid,
output wire s_eth2_tready,
output wire [PORT_W-1:0] m_eth2_tdata,
output wire m_eth2_tlast,
output wire m_eth2_tvalid,
input wire m_eth2_tready,
// Transport 3 (eth3)
input wire [PORT_W-1:0] s_eth3_tdata,
input wire s_eth3_tlast,
input wire s_eth3_tvalid,
output wire s_eth3_tready,
output wire [PORT_W-1:0] m_eth3_tdata,
output wire m_eth3_tlast,
output wire m_eth3_tvalid,
input wire m_eth3_tready,
// Transport 4 (eth4)
input wire [PORT_W-1:0] s_eth4_tdata,
input wire s_eth4_tlast,
input wire s_eth4_tvalid,
output wire s_eth4_tready,
output wire [PORT_W-1:0] m_eth4_tdata,
output wire m_eth4_tlast,
output wire m_eth4_tvalid,
input wire m_eth4_tready,
// Transport 5 (dma)
input wire [PORT_W-1:0] s_dma_tdata,
input wire s_dma_tlast,
input wire s_dma_tvalid,
output wire s_dma_tready,
output wire [PORT_W-1:0] m_dma_tdata,
output wire m_dma_tlast,
output wire m_dma_tvalid,
input wire m_dma_tready
);
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 512;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
localparam EP0_W = 512;
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
localparam EP1_W = 512;
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
localparam EP2_W = 512;
localparam EP2_MTU = BYTE_MTU - $clog2(EP2_W/8);
localparam EP3_W = 512;
localparam EP3_MTU = BYTE_MTU - $clog2(EP3_W/8);
wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
//---------------------------------------------------------------------------
// CHDR Crossbar
//---------------------------------------------------------------------------
wire [PORT_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready;
wire [PORT_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready;
wire [PORT_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready;
wire [PORT_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready;
wire [PORT_W-1:0] xb_to_ep2_tdata ;
wire xb_to_ep2_tlast ;
wire xb_to_ep2_tvalid;
wire xb_to_ep2_tready;
wire [PORT_W-1:0] ep2_to_xb_tdata ;
wire ep2_to_xb_tlast ;
wire ep2_to_xb_tvalid;
wire ep2_to_xb_tready;
wire [PORT_W-1:0] xb_to_ep3_tdata ;
wire xb_to_ep3_tlast ;
wire xb_to_ep3_tvalid;
wire xb_to_ep3_tready;
wire [PORT_W-1:0] ep3_to_xb_tdata ;
wire ep3_to_xb_tlast ;
wire ep3_to_xb_tvalid;
wire ep3_to_xb_tready;
chdr_crossbar_nxn #(
.PORT_W (PORT_W),
.NPORTS (10),
.CHDR_WIDTHS ({EP3_W, EP2_W, EP1_W, EP0_W, DMA_W, ETH4_W, ETH3_W, ETH2_W, ETH1_W, ETH0_W}),
.DEFAULT_PORT (0),
.ROUTES ({ 10'b1111111111,
10'b1111111111,
10'b1111111111,
10'b1111111111,
10'b1111100000,
10'b1111010000,
10'b1111001000,
10'b1111000100,
10'b1111000010,
10'b1111000001 }),
.BYTE_MTU (BYTE_MTU),
.ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"),
.NPORTS_MGMT (6),
.EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER)
) chdr_crossbar_nxn_i (
.clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst),
.device_id (device_id),
.s_axis_tdata ({ep3_to_xb_tdata , ep2_to_xb_tdata , ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , s_eth4_tdata , s_eth3_tdata , s_eth2_tdata , s_eth1_tdata , s_eth0_tdata }),
.s_axis_tlast ({ep3_to_xb_tlast , ep2_to_xb_tlast , ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , s_eth4_tlast , s_eth3_tlast , s_eth2_tlast , s_eth1_tlast , s_eth0_tlast }),
.s_axis_tvalid ({ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth4_tvalid, s_eth3_tvalid, s_eth2_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
.s_axis_tready ({ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth4_tready, s_eth3_tready, s_eth2_tready, s_eth1_tready, s_eth0_tready}),
.m_axis_tdata ({xb_to_ep3_tdata , xb_to_ep2_tdata , xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , m_eth4_tdata , m_eth3_tdata , m_eth2_tdata , m_eth1_tdata , m_eth0_tdata }),
.m_axis_tlast ({xb_to_ep3_tlast , xb_to_ep2_tlast , xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , m_eth4_tlast , m_eth3_tlast , m_eth2_tlast , m_eth1_tlast , m_eth0_tlast }),
.m_axis_tvalid ({xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth4_tvalid, m_eth3_tvalid, m_eth2_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
.m_axis_tready ({xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth4_tready, m_eth3_tready, m_eth2_tready, m_eth1_tready, m_eth0_tready}),
.ext_rtcfg_stb (1'h0),
.ext_rtcfg_addr (16'h0),
.ext_rtcfg_data (32'h0),
.ext_rtcfg_ack ()
);
//---------------------------------------------------------------------------
// Stream Endpoints
//---------------------------------------------------------------------------
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 8192;
localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER),
.CHDR_W (EP0_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
.NUM_DATA_O (1),
.INST_NUM (0),
.CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (EP0_MTU),
.REPORT_STRM_ERRS (1)
) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_chdr_rst (rfnoc_chdr_rst),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
.device_id (device_id),
.s_axis_chdr_tdata (xb_to_ep0_tdata),
.s_axis_chdr_tlast (xb_to_ep0_tlast),
.s_axis_chdr_tvalid (xb_to_ep0_tvalid),
.s_axis_chdr_tready (xb_to_ep0_tready),
.m_axis_chdr_tdata (ep0_to_xb_tdata),
.m_axis_chdr_tlast (ep0_to_xb_tlast),
.m_axis_chdr_tvalid (ep0_to_xb_tvalid),
.m_axis_chdr_tready (ep0_to_xb_tready),
.s_axis_data_tdata ({s_ep0_in0_tdata}),
.s_axis_data_tlast ({s_ep0_in0_tlast}),
.s_axis_data_tvalid ({s_ep0_in0_tvalid}),
.s_axis_data_tready ({s_ep0_in0_tready}),
.m_axis_data_tdata ({m_ep0_out0_tdata}),
.m_axis_data_tlast ({m_ep0_out0_tlast}),
.m_axis_data_tvalid ({m_ep0_out0_tvalid}),
.m_axis_data_tready ({m_ep0_out0_tready}),
.s_axis_ctrl_tdata (s_ep0_ctrl_tdata),
.s_axis_ctrl_tlast (s_ep0_ctrl_tlast),
.s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid),
.s_axis_ctrl_tready (s_ep0_ctrl_tready),
.m_axis_ctrl_tdata (m_ep0_ctrl_tdata),
.m_axis_ctrl_tlast (m_ep0_ctrl_tlast),
.m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid),
.m_axis_ctrl_tready (m_ep0_ctrl_tready),
.strm_seq_err_stb (),
.strm_data_err_stb (),
.strm_route_err_stb (),
.signal_data_err (1'b0)
);
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 8192;
localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER),
.CHDR_W (EP1_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
.NUM_DATA_O (1),
.INST_NUM (1),
.CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (EP1_MTU),
.REPORT_STRM_ERRS (1)
) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_chdr_rst (rfnoc_chdr_rst),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
.device_id (device_id),
.s_axis_chdr_tdata (xb_to_ep1_tdata),
.s_axis_chdr_tlast (xb_to_ep1_tlast),
.s_axis_chdr_tvalid (xb_to_ep1_tvalid),
.s_axis_chdr_tready (xb_to_ep1_tready),
.m_axis_chdr_tdata (ep1_to_xb_tdata),
.m_axis_chdr_tlast (ep1_to_xb_tlast),
.m_axis_chdr_tvalid (ep1_to_xb_tvalid),
.m_axis_chdr_tready (ep1_to_xb_tready),
.s_axis_data_tdata ({s_ep1_in0_tdata}),
.s_axis_data_tlast ({s_ep1_in0_tlast}),
.s_axis_data_tvalid ({s_ep1_in0_tvalid}),
.s_axis_data_tready ({s_ep1_in0_tready}),
.m_axis_data_tdata ({m_ep1_out0_tdata}),
.m_axis_data_tlast ({m_ep1_out0_tlast}),
.m_axis_data_tvalid ({m_ep1_out0_tvalid}),
.m_axis_data_tready ({m_ep1_out0_tready}),
.s_axis_ctrl_tdata (s_ep1_ctrl_tdata),
.s_axis_ctrl_tlast (s_ep1_ctrl_tlast),
.s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid),
.s_axis_ctrl_tready (s_ep1_ctrl_tready),
.m_axis_ctrl_tdata (m_ep1_ctrl_tdata),
.m_axis_ctrl_tlast (m_ep1_ctrl_tlast),
.m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid),
.m_axis_ctrl_tready (m_ep1_ctrl_tready),
.strm_seq_err_stb (),
.strm_data_err_stb (),
.strm_route_err_stb (),
.signal_data_err (1'b0)
);
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP2 = 8192;
localparam INGRESS_BUFF_SIZE_EP2 =
REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**EP2_MTU) ? EP2_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2);
wire [BLOCK_CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid;
wire m_ep2_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep2_in0_tdata;
wire s_ep2_in0_tlast;
wire s_ep2_in0_tvalid;
wire s_ep2_in0_tready;
wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata;
wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast;
wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid;
wire m_ep2_ctrl_tready, s_ep2_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER),
.CHDR_W (EP2_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
.NUM_DATA_O (1),
.INST_NUM (2),
.CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2),
.MTU (EP2_MTU),
.REPORT_STRM_ERRS (1)
) ep2_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_chdr_rst (rfnoc_chdr_rst),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
.device_id (device_id),
.s_axis_chdr_tdata (xb_to_ep2_tdata),
.s_axis_chdr_tlast (xb_to_ep2_tlast),
.s_axis_chdr_tvalid (xb_to_ep2_tvalid),
.s_axis_chdr_tready (xb_to_ep2_tready),
.m_axis_chdr_tdata (ep2_to_xb_tdata),
.m_axis_chdr_tlast (ep2_to_xb_tlast),
.m_axis_chdr_tvalid (ep2_to_xb_tvalid),
.m_axis_chdr_tready (ep2_to_xb_tready),
.s_axis_data_tdata ({s_ep2_in0_tdata}),
.s_axis_data_tlast ({s_ep2_in0_tlast}),
.s_axis_data_tvalid ({s_ep2_in0_tvalid}),
.s_axis_data_tready ({s_ep2_in0_tready}),
.m_axis_data_tdata ({m_ep2_out0_tdata}),
.m_axis_data_tlast ({m_ep2_out0_tlast}),
.m_axis_data_tvalid ({m_ep2_out0_tvalid}),
.m_axis_data_tready ({m_ep2_out0_tready}),
.s_axis_ctrl_tdata (s_ep2_ctrl_tdata),
.s_axis_ctrl_tlast (s_ep2_ctrl_tlast),
.s_axis_ctrl_tvalid (s_ep2_ctrl_tvalid),
.s_axis_ctrl_tready (s_ep2_ctrl_tready),
.m_axis_ctrl_tdata (m_ep2_ctrl_tdata),
.m_axis_ctrl_tlast (m_ep2_ctrl_tlast),
.m_axis_ctrl_tvalid (m_ep2_ctrl_tvalid),
.m_axis_ctrl_tready (m_ep2_ctrl_tready),
.strm_seq_err_stb (),
.strm_data_err_stb (),
.strm_route_err_stb (),
.signal_data_err (1'b0)
);
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP3 = 8192;
localparam INGRESS_BUFF_SIZE_EP3 =
REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**EP3_MTU) ? EP3_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3);
wire [BLOCK_CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid;
wire m_ep3_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep3_in0_tdata;
wire s_ep3_in0_tlast;
wire s_ep3_in0_tvalid;
wire s_ep3_in0_tready;
wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata;
wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast;
wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid;
wire m_ep3_ctrl_tready, s_ep3_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER),
.CHDR_W (EP3_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
.NUM_DATA_O (1),
.INST_NUM (3),
.CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3),
.MTU (EP3_MTU),
.REPORT_STRM_ERRS (1)
) ep3_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_chdr_rst (rfnoc_chdr_rst),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
.device_id (device_id),
.s_axis_chdr_tdata (xb_to_ep3_tdata),
.s_axis_chdr_tlast (xb_to_ep3_tlast),
.s_axis_chdr_tvalid (xb_to_ep3_tvalid),
.s_axis_chdr_tready (xb_to_ep3_tready),
.m_axis_chdr_tdata (ep3_to_xb_tdata),
.m_axis_chdr_tlast (ep3_to_xb_tlast),
.m_axis_chdr_tvalid (ep3_to_xb_tvalid),
.m_axis_chdr_tready (ep3_to_xb_tready),
.s_axis_data_tdata ({s_ep3_in0_tdata}),
.s_axis_data_tlast ({s_ep3_in0_tlast}),
.s_axis_data_tvalid ({s_ep3_in0_tvalid}),
.s_axis_data_tready ({s_ep3_in0_tready}),
.m_axis_data_tdata ({m_ep3_out0_tdata}),
.m_axis_data_tlast ({m_ep3_out0_tlast}),
.m_axis_data_tvalid ({m_ep3_out0_tvalid}),
.m_axis_data_tready ({m_ep3_out0_tready}),
.s_axis_ctrl_tdata (s_ep3_ctrl_tdata),
.s_axis_ctrl_tlast (s_ep3_ctrl_tlast),
.s_axis_ctrl_tvalid (s_ep3_ctrl_tvalid),
.s_axis_ctrl_tready (s_ep3_ctrl_tready),
.m_axis_ctrl_tdata (m_ep3_ctrl_tdata),
.m_axis_ctrl_tlast (m_ep3_ctrl_tlast),
.m_axis_ctrl_tvalid (m_ep3_ctrl_tvalid),
.m_axis_ctrl_tready (m_ep3_ctrl_tready),
.strm_seq_err_stb (),
.strm_data_err_stb (),
.strm_route_err_stb (),
.signal_data_err (1'b0)
);
//---------------------------------------------------------------------------
// Control Crossbar
//---------------------------------------------------------------------------
wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata;
wire m_core_ctrl_tlast, s_core_ctrl_tlast;
wire m_core_ctrl_tvalid, s_core_ctrl_tvalid;
wire m_core_ctrl_tready, s_core_ctrl_tready;
wire [31:0] m_radio0_ctrl_tdata, s_radio0_ctrl_tdata;
wire m_radio0_ctrl_tlast, s_radio0_ctrl_tlast;
wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid;
wire m_radio0_ctrl_tready, s_radio0_ctrl_tready;
wire [31:0] m_radio1_ctrl_tdata, s_radio1_ctrl_tdata;
wire m_radio1_ctrl_tlast, s_radio1_ctrl_tlast;
wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid;
wire m_radio1_ctrl_tready, s_radio1_ctrl_tready;
axis_ctrl_crossbar_nxn #(
.WIDTH (32),
.NPORTS (4),
.TOPOLOGY ("TORUS"),
.INGRESS_BUFF_SIZE(5),
.ROUTER_BUFF_SIZE (5),
.ROUTING_ALLOC ("WORMHOLE"),
.SWITCH_ALLOC ("PRIO")
) ctrl_xb_i (
.clk (rfnoc_ctrl_clk),
.reset (rfnoc_ctrl_rst),
.s_axis_tdata ({m_radio1_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
.s_axis_tvalid ({m_radio1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
.s_axis_tlast ({m_radio1_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
.s_axis_tready ({m_radio1_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
.m_axis_tdata ({s_radio1_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
.m_axis_tvalid ({s_radio1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
.m_axis_tlast ({s_radio1_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
.m_axis_tready ({s_radio1_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
.deadlock_detected()
);
//---------------------------------------------------------------------------
// RFNoC Core Kernel
//---------------------------------------------------------------------------
wire [(512*2)-1:0] rfnoc_core_config, rfnoc_core_status;
rfnoc_core_kernel #(
.PROTOVER (PROTOVER),
.DEVICE_TYPE (16'hA400),
.DEVICE_FAMILY ("ULTRASCALE"),
.SAFE_START_CLKS (0),
.NUM_BLOCKS (2),
.NUM_STREAM_ENDPOINTS(4),
.NUM_ENDPOINTS_CTRL (1),
.NUM_TRANSPORTS (6),
.NUM_EDGES (8),
.CHDR_XBAR_PRESENT (1),
.EDGE_TBL_FILE (EDGE_TBL_FILE)
) core_kernel_i (
.chdr_aclk (chdr_aclk),
.chdr_aclk_locked (1'b1),
.ctrl_aclk (ctrl_aclk),
.ctrl_aclk_locked (1'b1),
.core_arst (core_arst),
.core_chdr_clk (rfnoc_chdr_clk),
.core_chdr_rst (rfnoc_chdr_rst),
.core_ctrl_clk (rfnoc_ctrl_clk),
.core_ctrl_rst (rfnoc_ctrl_rst),
.s_axis_ctrl_tdata (s_core_ctrl_tdata),
.s_axis_ctrl_tlast (s_core_ctrl_tlast),
.s_axis_ctrl_tvalid (s_core_ctrl_tvalid),
.s_axis_ctrl_tready (s_core_ctrl_tready),
.m_axis_ctrl_tdata (m_core_ctrl_tdata),
.m_axis_ctrl_tlast (m_core_ctrl_tlast),
.m_axis_ctrl_tvalid (m_core_ctrl_tvalid),
.m_axis_ctrl_tready (m_core_ctrl_tready),
.device_id (device_id),
.rfnoc_core_config (rfnoc_core_config),
.rfnoc_core_status (rfnoc_core_status)
);
//---------------------------------------------------------------------------
// Blocks
//---------------------------------------------------------------------------
//-----------------------------------
// radio0
//-----------------------------------
wire radio0_radio_clk;
wire [BLOCK_CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
wire s_radio0_in_1_tready, s_radio0_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time
wire [ 63:0] radio0_radio_time;
// radio
wire [1023:0] radio0_radio_rx_data;
wire [ 31:0] radio0_radio_rx_stb;
wire [ 31:0] radio0_radio_rx_running;
wire [1023:0] radio0_radio_tx_data;
wire [ 31:0] radio0_radio_tx_stb;
wire [ 31:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (2),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2),
.NIPC (RADIO_NIPC),
.ITEM_W (32),
.CTRL_CLK_IDX (1),
.TB_CLK_IDX (4),
.MTU (BLOCK_MTU)
) b_radio0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.radio_clk (radio0_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
.m_ctrlport_req_wr (radio0_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio0_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio0_m_ctrlport_req_addr),
.m_ctrlport_req_data (radio0_m_ctrlport_req_data),
.m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en),
.m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time),
.m_ctrlport_req_time (radio0_m_ctrlport_req_time),
.m_ctrlport_resp_ack (radio0_m_ctrlport_resp_ack),
.m_ctrlport_resp_status(radio0_m_ctrlport_resp_status),
.m_ctrlport_resp_data(radio0_m_ctrlport_resp_data),
.radio_time (radio0_radio_time),
.radio_rx_data (radio0_radio_rx_data),
.radio_rx_stb (radio0_radio_rx_stb),
.radio_rx_running (radio0_radio_rx_running),
.radio_tx_data (radio0_radio_tx_data),
.radio_tx_stb (radio0_radio_tx_stb),
.radio_tx_running (radio0_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}),
.s_rfnoc_chdr_tready ({s_radio0_in_1_tready, s_radio0_in_0_tready}),
.m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }),
.m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast),
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast),
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
);
//-----------------------------------
// radio1
//-----------------------------------
wire radio1_radio_clk;
wire [BLOCK_CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ;
wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ;
wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid;
wire s_radio1_in_1_tready, s_radio1_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ;
wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ;
wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
wire m_radio1_out_1_tready, m_radio1_out_0_tready;
// ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 0:0] radio1_m_ctrlport_req_rd;
wire [ 19:0] radio1_m_ctrlport_req_addr;
wire [ 31:0] radio1_m_ctrlport_req_data;
wire [ 3:0] radio1_m_ctrlport_req_byte_en;
wire [ 0:0] radio1_m_ctrlport_req_has_time;
wire [ 63:0] radio1_m_ctrlport_req_time;
wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 31:0] radio1_m_ctrlport_resp_data;
// time
wire [ 63:0] radio1_radio_time;
// radio
wire [1023:0] radio1_radio_rx_data;
wire [ 31:0] radio1_radio_rx_stb;
wire [ 31:0] radio1_radio_rx_running;
wire [1023:0] radio1_radio_tx_data;
wire [ 31:0] radio1_radio_tx_stb;
wire [ 31:0] radio1_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (3),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2),
.NIPC (RADIO_NIPC),
.ITEM_W (32),
.CTRL_CLK_IDX (1),
.TB_CLK_IDX (4),
.MTU (BLOCK_MTU)
) b_radio1_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.radio_clk (radio1_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]),
.rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]),
.m_ctrlport_req_wr (radio1_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio1_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio1_m_ctrlport_req_addr),
.m_ctrlport_req_data (radio1_m_ctrlport_req_data),
.m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en),
.m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time),
.m_ctrlport_req_time (radio1_m_ctrlport_req_time),
.m_ctrlport_resp_ack (radio1_m_ctrlport_resp_ack),
.m_ctrlport_resp_status(radio1_m_ctrlport_resp_status),
.m_ctrlport_resp_data(radio1_m_ctrlport_resp_data),
.radio_time (radio1_radio_time),
.radio_rx_data (radio1_radio_rx_data),
.radio_rx_stb (radio1_radio_rx_stb),
.radio_rx_running (radio1_radio_rx_running),
.radio_tx_data (radio1_radio_tx_data),
.radio_tx_stb (radio1_radio_tx_stb),
.radio_tx_running (radio1_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}),
.s_rfnoc_chdr_tready ({s_radio1_in_1_tready, s_radio1_in_0_tready}),
.m_rfnoc_chdr_tdata ({m_radio1_out_1_tdata , m_radio1_out_0_tdata }),
.m_rfnoc_chdr_tlast ({m_radio1_out_1_tlast , m_radio1_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio1_out_1_tready, m_radio1_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast),
.s_rfnoc_ctrl_tvalid (s_radio1_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio1_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast),
.m_rfnoc_ctrl_tvalid (m_radio1_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio1_ctrl_tready)
);
//---------------------------------------------------------------------------
// Static Router
//---------------------------------------------------------------------------
assign s_radio0_in_0_tdata = m_ep0_out0_tdata;
assign s_radio0_in_0_tlast = m_ep0_out0_tlast;
assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid;
assign m_ep0_out0_tready = s_radio0_in_0_tready;
assign s_ep0_in0_tdata = m_radio0_out_0_tdata;
assign s_ep0_in0_tlast = m_radio0_out_0_tlast;
assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid;
assign m_radio0_out_0_tready = s_ep0_in0_tready;
assign s_radio0_in_1_tdata = m_ep1_out0_tdata;
assign s_radio0_in_1_tlast = m_ep1_out0_tlast;
assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid;
assign m_ep1_out0_tready = s_radio0_in_1_tready;
assign s_ep1_in0_tdata = m_radio0_out_1_tdata;
assign s_ep1_in0_tlast = m_radio0_out_1_tlast;
assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid;
assign m_radio0_out_1_tready = s_ep1_in0_tready;
assign s_radio1_in_0_tdata = m_ep2_out0_tdata;
assign s_radio1_in_0_tlast = m_ep2_out0_tlast;
assign s_radio1_in_0_tvalid = m_ep2_out0_tvalid;
assign m_ep2_out0_tready = s_radio1_in_0_tready;
assign s_ep2_in0_tdata = m_radio1_out_0_tdata;
assign s_ep2_in0_tlast = m_radio1_out_0_tlast;
assign s_ep2_in0_tvalid = m_radio1_out_0_tvalid;
assign m_radio1_out_0_tready = s_ep2_in0_tready;
assign s_radio1_in_1_tdata = m_ep3_out0_tdata;
assign s_radio1_in_1_tlast = m_ep3_out0_tlast;
assign s_radio1_in_1_tvalid = m_ep3_out0_tvalid;
assign m_ep3_out0_tready = s_radio1_in_1_tready;
assign s_ep3_in0_tdata = m_radio1_out_1_tdata;
assign s_ep3_in0_tlast = m_radio1_out_1_tlast;
assign s_ep3_in0_tvalid = m_radio1_out_1_tvalid;
assign m_radio1_out_1_tready = s_ep3_in0_tready;
//---------------------------------------------------------------------------
// Unused Ports
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
// Clock Domains
//---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk;
assign radio1_radio_clk = radio_clk;
//---------------------------------------------------------------------------
// IO Port Connection
//---------------------------------------------------------------------------
// Master/Slave Connections:
assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr;
assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd;
assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr;
assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data;
assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en;
assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time;
assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time;
assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack;
assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status;
assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data;
assign m_ctrlport_radio1_req_wr = radio1_m_ctrlport_req_wr;
assign m_ctrlport_radio1_req_rd = radio1_m_ctrlport_req_rd;
assign m_ctrlport_radio1_req_addr = radio1_m_ctrlport_req_addr;
assign m_ctrlport_radio1_req_data = radio1_m_ctrlport_req_data;
assign m_ctrlport_radio1_req_byte_en = radio1_m_ctrlport_req_byte_en;
assign m_ctrlport_radio1_req_has_time = radio1_m_ctrlport_req_has_time;
assign m_ctrlport_radio1_req_time = radio1_m_ctrlport_req_time;
assign radio1_m_ctrlport_resp_ack = m_ctrlport_radio1_resp_ack;
assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status;
assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data;
assign radio0_radio_rx_data = radio_rx_data_radio0;
assign radio0_radio_rx_stb = radio_rx_stb_radio0;
assign radio_rx_running_radio0 = radio0_radio_rx_running;
assign radio_tx_data_radio0 = radio0_radio_tx_data;
assign radio0_radio_tx_stb = radio_tx_stb_radio0;
assign radio_tx_running_radio0 = radio0_radio_tx_running;
assign radio1_radio_rx_data = radio_rx_data_radio1;
assign radio1_radio_rx_stb = radio_rx_stb_radio1;
assign radio_rx_running_radio1 = radio1_radio_rx_running;
assign radio_tx_data_radio1 = radio1_radio_tx_data;
assign radio1_radio_tx_stb = radio_tx_stb_radio1;
assign radio_tx_running_radio1 = radio1_radio_tx_running;
// Broadcaster/Listener Connections:
assign radio0_radio_time = radio_time;
assign radio1_radio_time = radio_time;
endmodule
`default_nettype wire
top/x400/x410_400_rfnoc_image_core.vh
-19
View File
@@ -1,19 +0,0 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for x410)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: x410_400_rfnoc_image_core.yml
//
`define CHDR_WIDTH 512
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/x400/x410_400_rfnoc_image_core.yml
-97
View File
@@ -1,97 +0,0 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 512 # Bit width of the CHDR bus for this image
device: 'x410' # USRP type
image_core_name: 'x410_400' # Name to use for the RFNoC Image Core files
default_target: 'X410_CG_400' # Default make target
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size_bytes: 524288 # Ingress buffer size for data
ep1:
ctrl: False
data: True
buff_size_bytes: 524288
ep2:
ctrl: False
data: True
buff_size_bytes: 524288
ep3:
ctrl: False
data: True
buff_size_bytes: 524288
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
radio0:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl # The clock that is used for the control
# interface. This is the default clock,
# so we could skip it.
timebase_clock: _device_.radio # The clock that is used for the timebase.
radio1:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl
timebase_clock: _device_.radio
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# RF A:0 TX
- { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
# RF A:0 RX
- { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
# RF A:1 TX
- { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 }
# RF A:1 RX
- { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 }
#
# RF B:0 TX
- { srcblk: ep2, srcport: out0, dstblk: radio1, dstport: in_0 }
# RF B:0 RX
- { srcblk: radio1, srcport: out_0, dstblk: ep2, dstport: in0 }
# RF B:1 TX
- { srcblk: ep3, srcport: out0, dstblk: radio1, dstport: in_1 }
# RF B:1 RX
- { srcblk: radio1, srcport: out_1, dstblk: ep3, dstport: in0 }
#
# BSP Connections
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect (Always "_device"_)
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
top/x400/x410_400_static_router.hex
-9
View File
@@ -1,9 +0,0 @@
00000008
00400140
01400040
00800141
01410080
00c00180
018000c0
01000181
01810100
top/x400/x410_CG_400_rfnoc_image_core.yml
+76
View File
@@ -0,0 +1,76 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 512 # Bit width of the CHDR bus for this image
device: 'x410' # USRP type
image_core_name: 'usrp_x410_fpga_CG_400' # Name to use for the generated output files
default_target: 'X410' # Default make target
inherit:
- 'yaml_include/x410_radio_base.yml'
- 'yaml_include/x4xx_cg_base.yml'
parameters:
RF_BW: 400
ENABLE_DRAM: False
NUM_DRAM_BANKS: 0
NUM_DRAM_CHANS: 0
DRAM_WIDTH: 64
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size_bytes: 524288 # Ingress buffer size for data
ep1:
ctrl: False
data: True
buff_size_bytes: 524288
ep2:
ctrl: False
data: True
buff_size_bytes: 524288
ep3:
ctrl: False
data: True
buff_size_bytes: 524288
# NoC blocks: Are defined in x410_radio_base.yml
# (as are their clock domain connections)
# ----------------------------------------------
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# RF A:0 TX
- { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
# RF A:0 RX
- { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
# RF A:1 TX
- { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 }
# RF A:1 RX
- { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 }
#
# RF B:0 TX
- { srcblk: ep2, srcport: out0, dstblk: radio1, dstport: in_0 }
# RF B:0 RX
- { srcblk: radio1, srcport: out_0, dstblk: ep2, dstport: in0 }
# RF B:1 TX
- { srcblk: ep3, srcport: out0, dstblk: radio1, dstport: in_1 }
# RF B:1 RX
- { srcblk: radio1, srcport: out_1, dstblk: ep3, dstport: in0 }
#
# BSP connections are inherited from YAML include files
# Clock domains are inherited from YAML include files
top/x400/x410_cg_200_rfnoc_image_core.yml → top/x400/x410_UC_200_rfnoc_image_core.yml
+45 -36
View File
@@ -1,60 +1,80 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 256 # Default bit width to use for CHDR buses
device: 'x410' # USRP type
image_core_name: 'x410_cg_200' # Name to use for the RFNoC Image Core files
default_target: 'X410_UC_200' # Default make target
version: '1.0' # File version
chdr_width: 256 # Bit width of the CHDR bus for this image
device: 'x410' # USRP type
image_core_name: 'usrp_x410_fpga_UC_200' # Name to use for the generated output files
default_target: 'X410' # Default make target
inherit:
- 'yaml_include/x410_radio_base.yml'
- 'yaml_include/x4xx_uc_base.yml'
parameters:
RF_BW: 200
ENABLE_DRAM: True
NUM_DRAM_BANKS: 1
NUM_DRAM_CHANS: 4
DRAM_WIDTH: 64
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
chdr_width: 256 # Bit width of CHDR bus connection to crossbar
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size_bytes: 262144 # Ingress buffer size for data
ep1:
chdr_width: 256
ctrl: False
data: True
buff_size_bytes: 262144
ep2:
chdr_width: 256
ctrl: False
data: True
buff_size_bytes: 262144
ep3:
chdr_width: 256
ctrl: False
data: True
buff_size_bytes: 262144
ep4:
chdr_width: 64
ctrl: False
data: True
buff_size_bytes: 32768
ep5:
chdr_width: 64
ctrl: False
data: True
buff_size_bytes: 32768
ep6:
chdr_width: 64
ctrl: False
data: True
buff_size_bytes: 32768
ep7:
chdr_width: 64
ctrl: False
data: True
buff_size_bytes: 32768
# A table of which crossbar routes to include
# -------------------------------------------
# Rows correspond to input ports and columns correspond to output ports.
# Entering a 1 includes and a 0 removes that route from the crossbar.
crossbar_routes:
# eth1 ep0 ep2 ep4 ep6
# dma ep1 ep3 ep5 ep7
- [ 1, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth1 (QSFP Port 1)
- [ 0, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # dma
- [ 1, 1, 0, 0, 0, 0, 1, 1, 1, 1 ] # ep0 (radio0.0)
- [ 1, 1, 0, 0, 0, 0, 1, 1, 1, 1 ] # ep1 (radio0.1)
- [ 1, 1, 0, 0, 0, 0, 1, 1, 1, 1 ] # ep2 (radio1.0)
- [ 1, 1, 0, 0, 0, 0, 1, 1, 1, 1 ] # ep3 (radio1.1)
- [ 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 ] # ep4 (replay0.0)
- [ 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 ] # ep5 (replay0.1)
- [ 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 ] # ep6 (replay0.2)
- [ 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 ] # ep7 (replay0.3)
# A list of all NoC blocks in design
# ----------------------------------
block_chdr_width: 64 # Bit width of the CHDR bus between blocks
@@ -72,10 +92,6 @@ noc_blocks:
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl # The clock that is used for the control
# interface. This is the default clock,
# so we could skip it.
timebase_clock: _device_.radio # The clock that is used for the timebase.
duc1:
block_desc: 'duc.yml'
parameters:
@@ -89,8 +105,6 @@ noc_blocks:
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl
timebase_clock: _device_.radio
replay0:
block_desc: 'replay.yml'
parameters:
@@ -143,13 +157,8 @@ connections:
- { srcblk: replay0, srcport: out_3, dstblk: ep7, dstport: in0 }
#
# BSP Connections
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 }
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 }
# Other BSP connections are inherited from YAML include files
# A list of all clock domain connections in design
# ------------------------------------------------
@@ -158,11 +167,11 @@ connections:
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
#
# Note that radio clocks are already defined in x410_radio_base.yml.
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
- { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
top/x400/x410_x4c_200_rfnoc_image_core.yml → top/x400/x410_X4_200_rfnoc_image_core.yml
+59 -31
View File
@@ -1,43 +1,64 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 256 # Default bit width to use for CHDR buses
device: 'x410' # USRP type
image_core_name: 'x410_x4c_200' # Name to use for the RFNoC Image Core files
default_target: 'X410_X4C_200' # Default make target
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'x410' # USRP type
image_core_name: 'usrp_x410_fpga_X4_200' # Name to use for the generated output files
default_target: 'X410' # Default make target
inherit:
- 'yaml_include/x410_radio_base.yml'
- 'yaml_include/x4xx_x4_base.yml'
parameters:
RF_BW: 200
ENABLE_DRAM: True
NUM_DRAM_BANKS: 1
NUM_DRAM_CHANS: 4
DRAM_WIDTH: 64
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
chdr_width: 256 # Bit width of CHDR bus connection to crossbar
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size_bytes: 262144 # Ingress buffer size for data
ep1:
chdr_width: 256
ctrl: False
data: True
buff_size_bytes: 262144
ep2:
chdr_width: 256
ctrl: False
data: True
buff_size_bytes: 262144
ep3:
chdr_width: 256
ctrl: False
data: True
buff_size_bytes: 262144
ep4:
ctrl: False
data: True
buff_size_bytes: 32768
ep5:
ctrl: False
data: True
buff_size_bytes: 32768
ep6:
ctrl: False
data: True
buff_size_bytes: 32768
ep7:
ctrl: False
data: True
buff_size_bytes: 32768
# A list of all NoC blocks in design
# ----------------------------------
block_chdr_width: 64 # Bit width of the CHDR bus between blocks
noc_blocks:
duc0: # NoC block name
block_desc: 'duc.yml' # Block device descriptor file
@@ -52,10 +73,6 @@ noc_blocks:
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl # The clock that is used for the control
# interface. This is the default clock,
# so we could skip it.
timebase_clock: _device_.radio # The clock that is used for the timebase.
duc1:
block_desc: 'duc.yml'
parameters:
@@ -69,8 +86,12 @@ noc_blocks:
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl
timebase_clock: _device_.radio
replay0:
block_desc: 'replay.yml'
parameters:
NUM_PORTS: 4
MEM_DATA_W: 64
MEM_ADDR_W: 32
# A list of all static connections in design
# ------------------------------------------
@@ -106,13 +127,19 @@ connections:
- { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
- { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 }
#
# Replay Connections
- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
- { srcblk: ep6, srcport: out0, dstblk: replay0, dstport: in_2 }
- { srcblk: replay0, srcport: out_2, dstblk: ep6, dstport: in0 }
- { srcblk: ep7, srcport: out0, dstblk: replay0, dstport: in_3 }
- { srcblk: replay0, srcport: out_3, dstblk: ep7, dstport: in0 }
#
# BSP Connections
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 }
# Other BSP connections are inherited from YAML include files
# A list of all clock domain connections in design
# ------------------------------------------------
@@ -121,10 +148,11 @@ connections:
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
#
# Note that radio clocks are already defined in x410_radio_base.yml.
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
top/x400/x410_200_rfnoc_image_core.yml → top/x400/x410_XG_200_rfnoc_image_core.yml
+22 -23
View File
@@ -1,15 +1,25 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'x410' # USRP type
image_core_name: 'x410_200' # Name to use for the RFNoC Image Core files
default_target: 'X410_X4_200' # Default make target
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'x410' # USRP type
image_core_name: 'usrp_x410_fpga_XG_200' # Name to use for the generated output files
default_target: 'X410' # Default make target
inherit:
- 'yaml_include/x410_radio_base.yml'
- 'yaml_include/x4xx_xg_base.yml'
parameters:
RF_BW: 200
ENABLE_DRAM: True
NUM_DRAM_BANKS: 1
NUM_DRAM_CHANS: 4
DRAM_WIDTH: 64
# A list of all stream endpoints in design
# ----------------------------------------
@@ -63,10 +73,6 @@ noc_blocks:
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl # The clock that is used for the control
# interface. This is the default clock,
# so we could skip it.
timebase_clock: _device_.radio # The clock that is used for the timebase.
duc1:
block_desc: 'duc.yml'
parameters:
@@ -80,8 +86,6 @@ noc_blocks:
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl
timebase_clock: _device_.radio
replay0:
block_desc: 'replay.yml'
parameters:
@@ -134,13 +138,8 @@ connections:
- { srcblk: replay0, srcport: out_3, dstblk: ep7, dstport: in0 }
#
# BSP Connections
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 }
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 }
# Other BSP connections are inherited from YAML include files
# A list of all clock domain connections in design
# ------------------------------------------------
@@ -149,11 +148,11 @@ connections:
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
#
# Note that radio clocks are already defined in x410_radio_base.yml.
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
top/x400/x410_cg_200_rfnoc_image_core.v
-1781
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top/x400/x410_cg_200_rfnoc_image_core.vh
-19
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@@ -1,19 +0,0 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for x410)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: x410_cg_200_rfnoc_image_core.yml
//
`define CHDR_WIDTH 256
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/x400/x410_cg_200_static_router.hex
-25
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@@ -1,25 +0,0 @@
00000018
00400240
024002c0
02c00280
02800040
00800241
024102c1
02c10281
02810080
00c00300
03000380
03800340
034000c0
01000301
03010381
03810341
03410100
014003c0
03c00140
018003c1
03c10180
01c003c2
03c201c0
020003c3
03c30200
top/x400/x410_x4c_200_rfnoc_image_core.v
-1225
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top/x400/x410_x4c_200_rfnoc_image_core.vh
-19
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@@ -1,19 +0,0 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for x410)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: x410_x4c_200_rfnoc_image_core.yml
//
`define CHDR_WIDTH 256
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/x400/x410_x4c_200_static_router.hex
-17
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@@ -1,17 +0,0 @@
00000010
00400140
014001c0
01c00180
01800040
00800141
014101c1
01c10181
01810080
00c00200
02000280
02800240
024000c0
01000201
02010281
02810241
02410100
top/x400/x440_1600_d_rfnoc_image_core.v
-1365
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top/x400/x440_1600_d_rfnoc_image_core.vh
-19
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@@ -1,19 +0,0 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for x440)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: x440_1600_d_rfnoc_image_core.yml
//
`define CHDR_WIDTH 512
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/x400/x440_1600_d_static_router.hex
-9
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@@ -1,9 +0,0 @@
00000008
00400140
01400040
00800180
01800080
00c001c0
01c000c0
01000200
02000100
top/x400/x440_1600_rfnoc_image_core.v
-805
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//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rfnoc_image_core (for x440)
//
// Description:
//
// The RFNoC Image Core contains the Verilog description of the RFNoC design
// to be loaded onto the FPGA.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: x440_1600_rfnoc_image_core.yml
//
`default_nettype none
module rfnoc_image_core #(
parameter [31:0] CHDR_W = 512,
parameter [31:0] PORT_W = 512,
parameter [31:0] ETH0_W = 64,
parameter [31:0] ETH1_W = 64,
parameter [31:0] ETH2_W = 64,
parameter [31:0] ETH3_W = 64,
parameter [31:0] ETH4_W = 64,
parameter [31:0] DMA_W = 64,
parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1
) (
// Clocks
input wire chdr_aclk,
input wire ctrl_aclk,
input wire core_arst,
input wire ce_clk,
input wire radio0_clk,
input wire radio1_clk,
input wire radio0_2x_clk,
input wire radio1_2x_clk,
input wire dram_clk,
// Basic
input wire [ 15:0] device_id,
// IO ports /////////////////////////
// ctrlport_radio0
output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 31:0] m_ctrlport_radio0_resp_data,
// ctrlport_radio1
output wire [ 0:0] m_ctrlport_radio1_req_wr,
output wire [ 0:0] m_ctrlport_radio1_req_rd,
output wire [ 19:0] m_ctrlport_radio1_req_addr,
output wire [ 31:0] m_ctrlport_radio1_req_data,
output wire [ 3:0] m_ctrlport_radio1_req_byte_en,
output wire [ 0:0] m_ctrlport_radio1_req_has_time,
output wire [ 63:0] m_ctrlport_radio1_req_time,
input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 31:0] m_ctrlport_radio1_resp_data,
// time0
input wire [ 63:0] radio_time0,
// time1
input wire [ 63:0] radio_time1,
// radio0
input wire [1023:0] radio_rx_data_radio0,
input wire [ 31:0] radio_rx_stb_radio0,
output wire [ 31:0] radio_rx_running_radio0,
output wire [1023:0] radio_tx_data_radio0,
input wire [ 31:0] radio_tx_stb_radio0,
output wire [ 31:0] radio_tx_running_radio0,
// radio1
input wire [1023:0] radio_rx_data_radio1,
input wire [ 31:0] radio_rx_stb_radio1,
output wire [ 31:0] radio_rx_running_radio1,
output wire [1023:0] radio_tx_data_radio1,
input wire [ 31:0] radio_tx_stb_radio1,
output wire [ 31:0] radio_tx_running_radio1,
// dram0
input wire [ 0:0] dram0_axi_rst,
output wire [ 7:0] dram0_m_axi_awid,
output wire [ 383:0] dram0_m_axi_awaddr,
output wire [ 63:0] dram0_m_axi_awlen,
output wire [ 23:0] dram0_m_axi_awsize,
output wire [ 15:0] dram0_m_axi_awburst,
output wire [ 7:0] dram0_m_axi_awlock,
output wire [ 31:0] dram0_m_axi_awcache,
output wire [ 23:0] dram0_m_axi_awprot,
output wire [ 31:0] dram0_m_axi_awqos,
output wire [ 31:0] dram0_m_axi_awregion,
output wire [ 7:0] dram0_m_axi_awuser,
output wire [ 7:0] dram0_m_axi_awvalid,
input wire [ 7:0] dram0_m_axi_awready,
output wire [4191:0] dram0_m_axi_wdata,
output wire [ 511:0] dram0_m_axi_wstrb,
output wire [ 7:0] dram0_m_axi_wlast,
output wire [ 7:0] dram0_m_axi_wuser,
output wire [ 7:0] dram0_m_axi_wvalid,
input wire [ 7:0] dram0_m_axi_wready,
input wire [ 7:0] dram0_m_axi_bid,
input wire [ 15:0] dram0_m_axi_bresp,
input wire [ 7:0] dram0_m_axi_buser,
input wire [ 7:0] dram0_m_axi_bvalid,
output wire [ 7:0] dram0_m_axi_bready,
output wire [ 7:0] dram0_m_axi_arid,
output wire [ 383:0] dram0_m_axi_araddr,
output wire [ 63:0] dram0_m_axi_arlen,
output wire [ 23:0] dram0_m_axi_arsize,
output wire [ 15:0] dram0_m_axi_arburst,
output wire [ 7:0] dram0_m_axi_arlock,
output wire [ 31:0] dram0_m_axi_arcache,
output wire [ 31:0] dram0_m_axi_arprot,
output wire [ 31:0] dram0_m_axi_arqos,
output wire [ 31:0] dram0_m_axi_arregion,
output wire [ 7:0] dram0_m_axi_aruser,
output wire [ 7:0] dram0_m_axi_arvalid,
input wire [ 7:0] dram0_m_axi_arready,
input wire [ 7:0] dram0_m_axi_rid,
input wire [4191:0] dram0_m_axi_rdata,
input wire [ 15:0] dram0_m_axi_rresp,
input wire [ 7:0] dram0_m_axi_rlast,
input wire [ 7:0] dram0_m_axi_ruser,
input wire [ 7:0] dram0_m_axi_rvalid,
output wire [ 7:0] dram0_m_axi_rready,
// dram1
input wire [ 0:0] dram1_axi_rst,
output wire [ 7:0] dram1_m_axi_awid,
output wire [ 383:0] dram1_m_axi_awaddr,
output wire [ 63:0] dram1_m_axi_awlen,
output wire [ 23:0] dram1_m_axi_awsize,
output wire [ 15:0] dram1_m_axi_awburst,
output wire [ 7:0] dram1_m_axi_awlock,
output wire [ 31:0] dram1_m_axi_awcache,
output wire [ 23:0] dram1_m_axi_awprot,
output wire [ 31:0] dram1_m_axi_awqos,
output wire [ 31:0] dram1_m_axi_awregion,
output wire [ 7:0] dram1_m_axi_awuser,
output wire [ 7:0] dram1_m_axi_awvalid,
input wire [ 7:0] dram1_m_axi_awready,
output wire [4191:0] dram1_m_axi_wdata,
output wire [ 511:0] dram1_m_axi_wstrb,
output wire [ 7:0] dram1_m_axi_wlast,
output wire [ 7:0] dram1_m_axi_wuser,
output wire [ 7:0] dram1_m_axi_wvalid,
input wire [ 7:0] dram1_m_axi_wready,
input wire [ 7:0] dram1_m_axi_bid,
input wire [ 15:0] dram1_m_axi_bresp,
input wire [ 7:0] dram1_m_axi_buser,
input wire [ 7:0] dram1_m_axi_bvalid,
output wire [ 7:0] dram1_m_axi_bready,
output wire [ 7:0] dram1_m_axi_arid,
output wire [ 383:0] dram1_m_axi_araddr,
output wire [ 63:0] dram1_m_axi_arlen,
output wire [ 23:0] dram1_m_axi_arsize,
output wire [ 15:0] dram1_m_axi_arburst,
output wire [ 7:0] dram1_m_axi_arlock,
output wire [ 31:0] dram1_m_axi_arcache,
output wire [ 31:0] dram1_m_axi_arprot,
output wire [ 31:0] dram1_m_axi_arqos,
output wire [ 31:0] dram1_m_axi_arregion,
output wire [ 7:0] dram1_m_axi_aruser,
output wire [ 7:0] dram1_m_axi_arvalid,
input wire [ 7:0] dram1_m_axi_arready,
input wire [ 7:0] dram1_m_axi_rid,
input wire [4191:0] dram1_m_axi_rdata,
input wire [ 15:0] dram1_m_axi_rresp,
input wire [ 7:0] dram1_m_axi_rlast,
input wire [ 7:0] dram1_m_axi_ruser,
input wire [ 7:0] dram1_m_axi_rvalid,
output wire [ 7:0] dram1_m_axi_rready,
// Transport Adapters ///////////////
// Transport 0 (eth0)
input wire [PORT_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast,
input wire s_eth0_tvalid,
output wire s_eth0_tready,
output wire [PORT_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast,
output wire m_eth0_tvalid,
input wire m_eth0_tready,
// Transport 1 (eth1)
input wire [PORT_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast,
input wire s_eth1_tvalid,
output wire s_eth1_tready,
output wire [PORT_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast,
output wire m_eth1_tvalid,
input wire m_eth1_tready,
// Transport 2 (eth2)
input wire [PORT_W-1:0] s_eth2_tdata,
input wire s_eth2_tlast,
input wire s_eth2_tvalid,
output wire s_eth2_tready,
output wire [PORT_W-1:0] m_eth2_tdata,
output wire m_eth2_tlast,
output wire m_eth2_tvalid,
input wire m_eth2_tready,
// Transport 3 (eth3)
input wire [PORT_W-1:0] s_eth3_tdata,
input wire s_eth3_tlast,
input wire s_eth3_tvalid,
output wire s_eth3_tready,
output wire [PORT_W-1:0] m_eth3_tdata,
output wire m_eth3_tlast,
output wire m_eth3_tvalid,
input wire m_eth3_tready,
// Transport 4 (eth4)
input wire [PORT_W-1:0] s_eth4_tdata,
input wire s_eth4_tlast,
input wire s_eth4_tvalid,
output wire s_eth4_tready,
output wire [PORT_W-1:0] m_eth4_tdata,
output wire m_eth4_tlast,
output wire m_eth4_tvalid,
input wire m_eth4_tready,
// Transport 5 (dma)
input wire [PORT_W-1:0] s_dma_tdata,
input wire s_dma_tlast,
input wire s_dma_tvalid,
output wire s_dma_tready,
output wire [PORT_W-1:0] m_dma_tdata,
output wire m_dma_tlast,
output wire m_dma_tvalid,
input wire m_dma_tready
);
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 512;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
localparam EP0_W = 512;
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
localparam EP1_W = 512;
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
//---------------------------------------------------------------------------
// CHDR Crossbar
//---------------------------------------------------------------------------
wire [PORT_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready;
wire [PORT_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready;
wire [PORT_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready;
wire [PORT_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready;
chdr_crossbar_nxn #(
.PORT_W (PORT_W),
.NPORTS (8),
.CHDR_WIDTHS ({EP1_W, EP0_W, DMA_W, ETH4_W, ETH3_W, ETH2_W, ETH1_W, ETH0_W}),
.DEFAULT_PORT (0),
.ROUTES ({ 8'b00110001,
8'b00110001,
8'b11100000,
8'b11010000,
8'b00000000,
8'b00000000,
8'b00000000,
8'b11000001 }),
.BYTE_MTU (BYTE_MTU),
.ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"),
.NPORTS_MGMT (6),
.EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER)
) chdr_crossbar_nxn_i (
.clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst),
.device_id (device_id),
.s_axis_tdata ({ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , s_eth4_tdata , {PORT_W{1'b0}}, {PORT_W{1'b0}}, {PORT_W{1'b0}}, s_eth0_tdata }),
.s_axis_tlast ({ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , s_eth4_tlast , 1'b0, 1'b0, 1'b0, s_eth0_tlast }),
.s_axis_tvalid ({ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth4_tvalid, 1'b0, 1'b0, 1'b0, s_eth0_tvalid}),
.s_axis_tready ({ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth4_tready, 1'bZ, 1'bZ, 1'bZ, s_eth0_tready}),
.m_axis_tdata ({xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , m_eth4_tdata , {PORT_W{1'bZ}}, {PORT_W{1'bZ}}, {PORT_W{1'bZ}}, m_eth0_tdata }),
.m_axis_tlast ({xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , m_eth4_tlast , 1'bZ, 1'bZ, 1'bZ, m_eth0_tlast }),
.m_axis_tvalid ({xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth4_tvalid, 1'bZ, 1'bZ, 1'bZ, m_eth0_tvalid}),
.m_axis_tready ({xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth4_tready, 1'b1, 1'b1, 1'b1, m_eth0_tready}),
.ext_rtcfg_stb (1'h0),
.ext_rtcfg_addr (16'h0),
.ext_rtcfg_data (32'h0),
.ext_rtcfg_ack ()
);
//---------------------------------------------------------------------------
// Stream Endpoints
//---------------------------------------------------------------------------
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 32768;
localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER),
.CHDR_W (EP0_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
.NUM_DATA_O (1),
.INST_NUM (0),
.CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (EP0_MTU),
.REPORT_STRM_ERRS (1)
) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_chdr_rst (rfnoc_chdr_rst),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
.device_id (device_id),
.s_axis_chdr_tdata (xb_to_ep0_tdata),
.s_axis_chdr_tlast (xb_to_ep0_tlast),
.s_axis_chdr_tvalid (xb_to_ep0_tvalid),
.s_axis_chdr_tready (xb_to_ep0_tready),
.m_axis_chdr_tdata (ep0_to_xb_tdata),
.m_axis_chdr_tlast (ep0_to_xb_tlast),
.m_axis_chdr_tvalid (ep0_to_xb_tvalid),
.m_axis_chdr_tready (ep0_to_xb_tready),
.s_axis_data_tdata ({s_ep0_in0_tdata}),
.s_axis_data_tlast ({s_ep0_in0_tlast}),
.s_axis_data_tvalid ({s_ep0_in0_tvalid}),
.s_axis_data_tready ({s_ep0_in0_tready}),
.m_axis_data_tdata ({m_ep0_out0_tdata}),
.m_axis_data_tlast ({m_ep0_out0_tlast}),
.m_axis_data_tvalid ({m_ep0_out0_tvalid}),
.m_axis_data_tready ({m_ep0_out0_tready}),
.s_axis_ctrl_tdata (s_ep0_ctrl_tdata),
.s_axis_ctrl_tlast (s_ep0_ctrl_tlast),
.s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid),
.s_axis_ctrl_tready (s_ep0_ctrl_tready),
.m_axis_ctrl_tdata (m_ep0_ctrl_tdata),
.m_axis_ctrl_tlast (m_ep0_ctrl_tlast),
.m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid),
.m_axis_ctrl_tready (m_ep0_ctrl_tready),
.strm_seq_err_stb (),
.strm_data_err_stb (),
.strm_route_err_stb (),
.signal_data_err (1'b0)
);
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 32768;
localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER),
.CHDR_W (EP1_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
.NUM_DATA_O (1),
.INST_NUM (1),
.CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (EP1_MTU),
.REPORT_STRM_ERRS (1)
) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_chdr_rst (rfnoc_chdr_rst),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
.device_id (device_id),
.s_axis_chdr_tdata (xb_to_ep1_tdata),
.s_axis_chdr_tlast (xb_to_ep1_tlast),
.s_axis_chdr_tvalid (xb_to_ep1_tvalid),
.s_axis_chdr_tready (xb_to_ep1_tready),
.m_axis_chdr_tdata (ep1_to_xb_tdata),
.m_axis_chdr_tlast (ep1_to_xb_tlast),
.m_axis_chdr_tvalid (ep1_to_xb_tvalid),
.m_axis_chdr_tready (ep1_to_xb_tready),
.s_axis_data_tdata ({s_ep1_in0_tdata}),
.s_axis_data_tlast ({s_ep1_in0_tlast}),
.s_axis_data_tvalid ({s_ep1_in0_tvalid}),
.s_axis_data_tready ({s_ep1_in0_tready}),
.m_axis_data_tdata ({m_ep1_out0_tdata}),
.m_axis_data_tlast ({m_ep1_out0_tlast}),
.m_axis_data_tvalid ({m_ep1_out0_tvalid}),
.m_axis_data_tready ({m_ep1_out0_tready}),
.s_axis_ctrl_tdata (s_ep1_ctrl_tdata),
.s_axis_ctrl_tlast (s_ep1_ctrl_tlast),
.s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid),
.s_axis_ctrl_tready (s_ep1_ctrl_tready),
.m_axis_ctrl_tdata (m_ep1_ctrl_tdata),
.m_axis_ctrl_tlast (m_ep1_ctrl_tlast),
.m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid),
.m_axis_ctrl_tready (m_ep1_ctrl_tready),
.strm_seq_err_stb (),
.strm_data_err_stb (),
.strm_route_err_stb (),
.signal_data_err (1'b0)
);
//---------------------------------------------------------------------------
// Control Crossbar
//---------------------------------------------------------------------------
wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata;
wire m_core_ctrl_tlast, s_core_ctrl_tlast;
wire m_core_ctrl_tvalid, s_core_ctrl_tvalid;
wire m_core_ctrl_tready, s_core_ctrl_tready;
wire [31:0] m_radio0_ctrl_tdata, s_radio0_ctrl_tdata;
wire m_radio0_ctrl_tlast, s_radio0_ctrl_tlast;
wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid;
wire m_radio0_ctrl_tready, s_radio0_ctrl_tready;
wire [31:0] m_radio1_ctrl_tdata, s_radio1_ctrl_tdata;
wire m_radio1_ctrl_tlast, s_radio1_ctrl_tlast;
wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid;
wire m_radio1_ctrl_tready, s_radio1_ctrl_tready;
axis_ctrl_crossbar_nxn #(
.WIDTH (32),
.NPORTS (4),
.TOPOLOGY ("TORUS"),
.INGRESS_BUFF_SIZE(5),
.ROUTER_BUFF_SIZE (5),
.ROUTING_ALLOC ("WORMHOLE"),
.SWITCH_ALLOC ("PRIO")
) ctrl_xb_i (
.clk (rfnoc_ctrl_clk),
.reset (rfnoc_ctrl_rst),
.s_axis_tdata ({m_radio1_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
.s_axis_tvalid ({m_radio1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
.s_axis_tlast ({m_radio1_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
.s_axis_tready ({m_radio1_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
.m_axis_tdata ({s_radio1_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
.m_axis_tvalid ({s_radio1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
.m_axis_tlast ({s_radio1_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
.m_axis_tready ({s_radio1_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
.deadlock_detected()
);
//---------------------------------------------------------------------------
// RFNoC Core Kernel
//---------------------------------------------------------------------------
wire [(512*2)-1:0] rfnoc_core_config, rfnoc_core_status;
rfnoc_core_kernel #(
.PROTOVER (PROTOVER),
.DEVICE_TYPE (16'hA400),
.DEVICE_FAMILY ("ULTRASCALE"),
.SAFE_START_CLKS (0),
.NUM_BLOCKS (2),
.NUM_STREAM_ENDPOINTS(2),
.NUM_ENDPOINTS_CTRL (1),
.NUM_TRANSPORTS (6),
.NUM_EDGES (4),
.CHDR_XBAR_PRESENT (1),
.EDGE_TBL_FILE (EDGE_TBL_FILE)
) core_kernel_i (
.chdr_aclk (chdr_aclk),
.chdr_aclk_locked (1'b1),
.ctrl_aclk (ctrl_aclk),
.ctrl_aclk_locked (1'b1),
.core_arst (core_arst),
.core_chdr_clk (rfnoc_chdr_clk),
.core_chdr_rst (rfnoc_chdr_rst),
.core_ctrl_clk (rfnoc_ctrl_clk),
.core_ctrl_rst (rfnoc_ctrl_rst),
.s_axis_ctrl_tdata (s_core_ctrl_tdata),
.s_axis_ctrl_tlast (s_core_ctrl_tlast),
.s_axis_ctrl_tvalid (s_core_ctrl_tvalid),
.s_axis_ctrl_tready (s_core_ctrl_tready),
.m_axis_ctrl_tdata (m_core_ctrl_tdata),
.m_axis_ctrl_tlast (m_core_ctrl_tlast),
.m_axis_ctrl_tvalid (m_core_ctrl_tvalid),
.m_axis_ctrl_tready (m_core_ctrl_tready),
.device_id (device_id),
.rfnoc_core_config (rfnoc_core_config),
.rfnoc_core_status (rfnoc_core_status)
);
//---------------------------------------------------------------------------
// Blocks
//---------------------------------------------------------------------------
//-----------------------------------
// radio0
//-----------------------------------
wire radio0_radio_clk;
wire [BLOCK_CHDR_W-1:0] s_radio0_in_0_tdata ;
wire s_radio0_in_0_tlast ;
wire s_radio0_in_0_tvalid;
wire s_radio0_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_radio0_out_0_tdata ;
wire m_radio0_out_0_tlast ;
wire m_radio0_out_0_tvalid;
wire m_radio0_out_0_tready;
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time
wire [ 63:0] radio0_radio_time;
// radio
wire [1023:0] radio0_radio_rx_data;
wire [ 31:0] radio0_radio_rx_stb;
wire [ 31:0] radio0_radio_rx_running;
wire [1023:0] radio0_radio_tx_data;
wire [ 31:0] radio0_radio_tx_stb;
wire [ 31:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (2),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (1),
.NIPC (RADIO_NIPC),
.ITEM_W (32),
.CTRL_CLK_IDX (1),
.TB_CLK_IDX (4),
.MTU (BLOCK_MTU)
) b_radio0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.radio_clk (radio0_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
.m_ctrlport_req_wr (radio0_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio0_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio0_m_ctrlport_req_addr),
.m_ctrlport_req_data (radio0_m_ctrlport_req_data),
.m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en),
.m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time),
.m_ctrlport_req_time (radio0_m_ctrlport_req_time),
.m_ctrlport_resp_ack (radio0_m_ctrlport_resp_ack),
.m_ctrlport_resp_status(radio0_m_ctrlport_resp_status),
.m_ctrlport_resp_data(radio0_m_ctrlport_resp_data),
.radio_time (radio0_radio_time),
.radio_rx_data (radio0_radio_rx_data),
.radio_rx_stb (radio0_radio_rx_stb),
.radio_rx_running (radio0_radio_rx_running),
.radio_tx_data (radio0_radio_tx_data),
.radio_tx_stb (radio0_radio_tx_stb),
.radio_tx_running (radio0_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio0_in_0_tvalid}),
.s_rfnoc_chdr_tready ({s_radio0_in_0_tready}),
.m_rfnoc_chdr_tdata ({m_radio0_out_0_tdata }),
.m_rfnoc_chdr_tlast ({m_radio0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast),
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast),
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
);
//-----------------------------------
// radio1
//-----------------------------------
wire radio1_radio_clk;
wire [BLOCK_CHDR_W-1:0] s_radio1_in_0_tdata ;
wire s_radio1_in_0_tlast ;
wire s_radio1_in_0_tvalid;
wire s_radio1_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_radio1_out_0_tdata ;
wire m_radio1_out_0_tlast ;
wire m_radio1_out_0_tvalid;
wire m_radio1_out_0_tready;
// ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 0:0] radio1_m_ctrlport_req_rd;
wire [ 19:0] radio1_m_ctrlport_req_addr;
wire [ 31:0] radio1_m_ctrlport_req_data;
wire [ 3:0] radio1_m_ctrlport_req_byte_en;
wire [ 0:0] radio1_m_ctrlport_req_has_time;
wire [ 63:0] radio1_m_ctrlport_req_time;
wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 31:0] radio1_m_ctrlport_resp_data;
// time
wire [ 63:0] radio1_radio_time;
// radio
wire [1023:0] radio1_radio_rx_data;
wire [ 31:0] radio1_radio_rx_stb;
wire [ 31:0] radio1_radio_rx_running;
wire [1023:0] radio1_radio_tx_data;
wire [ 31:0] radio1_radio_tx_stb;
wire [ 31:0] radio1_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (3),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (1),
.NIPC (RADIO_NIPC),
.ITEM_W (32),
.CTRL_CLK_IDX (1),
.TB_CLK_IDX (5),
.MTU (BLOCK_MTU)
) b_radio1_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.radio_clk (radio1_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]),
.rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]),
.m_ctrlport_req_wr (radio1_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio1_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio1_m_ctrlport_req_addr),
.m_ctrlport_req_data (radio1_m_ctrlport_req_data),
.m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en),
.m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time),
.m_ctrlport_req_time (radio1_m_ctrlport_req_time),
.m_ctrlport_resp_ack (radio1_m_ctrlport_resp_ack),
.m_ctrlport_resp_status(radio1_m_ctrlport_resp_status),
.m_ctrlport_resp_data(radio1_m_ctrlport_resp_data),
.radio_time (radio1_radio_time),
.radio_rx_data (radio1_radio_rx_data),
.radio_rx_stb (radio1_radio_rx_stb),
.radio_rx_running (radio1_radio_rx_running),
.radio_tx_data (radio1_radio_tx_data),
.radio_tx_stb (radio1_radio_tx_stb),
.radio_tx_running (radio1_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio1_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio1_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio1_in_0_tvalid}),
.s_rfnoc_chdr_tready ({s_radio1_in_0_tready}),
.m_rfnoc_chdr_tdata ({m_radio1_out_0_tdata }),
.m_rfnoc_chdr_tlast ({m_radio1_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio1_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio1_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast),
.s_rfnoc_ctrl_tvalid (s_radio1_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio1_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast),
.m_rfnoc_ctrl_tvalid (m_radio1_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio1_ctrl_tready)
);
//---------------------------------------------------------------------------
// Static Router
//---------------------------------------------------------------------------
assign s_radio0_in_0_tdata = m_ep0_out0_tdata;
assign s_radio0_in_0_tlast = m_ep0_out0_tlast;
assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid;
assign m_ep0_out0_tready = s_radio0_in_0_tready;
assign s_ep0_in0_tdata = m_radio0_out_0_tdata;
assign s_ep0_in0_tlast = m_radio0_out_0_tlast;
assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid;
assign m_radio0_out_0_tready = s_ep0_in0_tready;
assign s_radio1_in_0_tdata = m_ep1_out0_tdata;
assign s_radio1_in_0_tlast = m_ep1_out0_tlast;
assign s_radio1_in_0_tvalid = m_ep1_out0_tvalid;
assign m_ep1_out0_tready = s_radio1_in_0_tready;
assign s_ep1_in0_tdata = m_radio1_out_0_tdata;
assign s_ep1_in0_tlast = m_radio1_out_0_tlast;
assign s_ep1_in0_tvalid = m_radio1_out_0_tvalid;
assign m_radio1_out_0_tready = s_ep1_in0_tready;
//---------------------------------------------------------------------------
// Unused Ports
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
// Clock Domains
//---------------------------------------------------------------------------
assign radio0_radio_clk = radio0_clk;
assign radio1_radio_clk = radio1_clk;
//---------------------------------------------------------------------------
// IO Port Connection
//---------------------------------------------------------------------------
// Master/Slave Connections:
assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr;
assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd;
assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr;
assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data;
assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en;
assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time;
assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time;
assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack;
assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status;
assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data;
assign m_ctrlport_radio1_req_wr = radio1_m_ctrlport_req_wr;
assign m_ctrlport_radio1_req_rd = radio1_m_ctrlport_req_rd;
assign m_ctrlport_radio1_req_addr = radio1_m_ctrlport_req_addr;
assign m_ctrlport_radio1_req_data = radio1_m_ctrlport_req_data;
assign m_ctrlport_radio1_req_byte_en = radio1_m_ctrlport_req_byte_en;
assign m_ctrlport_radio1_req_has_time = radio1_m_ctrlport_req_has_time;
assign m_ctrlport_radio1_req_time = radio1_m_ctrlport_req_time;
assign radio1_m_ctrlport_resp_ack = m_ctrlport_radio1_resp_ack;
assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status;
assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data;
assign radio0_radio_rx_data = radio_rx_data_radio0;
assign radio0_radio_rx_stb = radio_rx_stb_radio0;
assign radio_rx_running_radio0 = radio0_radio_rx_running;
assign radio_tx_data_radio0 = radio0_radio_tx_data;
assign radio0_radio_tx_stb = radio_tx_stb_radio0;
assign radio_tx_running_radio0 = radio0_radio_tx_running;
assign radio1_radio_rx_data = radio_rx_data_radio1;
assign radio1_radio_rx_stb = radio_rx_stb_radio1;
assign radio_rx_running_radio1 = radio1_radio_rx_running;
assign radio_tx_data_radio1 = radio1_radio_tx_data;
assign radio1_radio_tx_stb = radio_tx_stb_radio1;
assign radio_tx_running_radio1 = radio1_radio_tx_running;
// Broadcaster/Listener Connections:
assign radio0_radio_time = radio_time0;
assign radio1_radio_time = radio_time1;
endmodule
`default_nettype wire
top/x400/x440_1600_rfnoc_image_core.vh
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//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for x440)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: x440_1600_rfnoc_image_core.yml
//
`define CHDR_WIDTH 512
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/x400/x440_1600_rfnoc_image_core.yml
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# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 512 # Bit width of the CHDR bus for this image
device: 'x440' # USRP type
image_core_name: 'x440_1600' # Name to use for the RFNoC Image Core files
default_target: 'X440_CG_1600' # Default make target
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size_bytes: 2097152 # Ingress buffer size for data
ep1:
ctrl: False
data: True
buff_size_bytes: 2097152
# A table of which crossbar routes to include
# -------------------------------------------
# Rows correspond to input ports and columns correspond to output ports.
# Entering a 1 includes and a 0 removes that route from the crossbar.
crossbar_routes:
# eth0 eth2 eth4 ep0
# eth1 eth3 dma ep1
- [ 1, 0, 0, 0, 0, 0, 1, 1 ] # eth0 (QSFP Port 0)
- [ 0, 0, 0, 0, 0, 0, 0, 0 ] # eth1 (NC)
- [ 0, 0, 0, 0, 0, 0, 0, 0 ] # eth2 (NC)
- [ 0, 0, 0, 0, 0, 0, 0, 0 ] # eth3 (NC)
- [ 0, 0, 0, 0, 1, 0, 1, 1 ] # eth4 (QSFP Port 1)
- [ 0, 0, 0, 0, 0, 1, 1, 1 ] # dma
- [ 1, 0, 0, 0, 1, 1, 0, 0 ] # ep0 (radio0.0)
- [ 1, 0, 0, 0, 1, 1, 0, 0 ] # ep1 (radio1.0)
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
radio0:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 1
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl # The clock that is used for the control
# interface. This is the default clock,
# so we could skip it.
timebase_clock: _device_.radio0 # The clock that is used for the timebase.
radio1:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 1
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl
timebase_clock: _device_.radio1
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# RF A:0 TX
- { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
# RF A:0 RX
- { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
#
# RF B:0 TX
- { srcblk: ep1, srcport: out0, dstblk: radio1, dstport: in_0 }
# RF B:0 RX
- { srcblk: radio1, srcport: out_0, dstblk: ep1, dstport: in0 }
#
# BSP Connections
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: time0, dstblk: radio0, dstport: time }
- { srcblk: _device_, srcport: time1, dstblk: radio1, dstport: time }
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect (Always "_device"_)
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
top/x400/x440_1600_static_router.hex
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00000004
004000c0
00c00040
00800100
01000080
top/x400/x440_200_rfnoc_image_core.v
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top/x400/x440_200_rfnoc_image_core.vh
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//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for x440)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: x440_200_rfnoc_image_core.yml
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/x400/x440_200_static_router.hex
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00000020
004002c0
02c00240
02400300
03000040
008002c1
02c10241
02410301
03010080
00c002c2
02c20242
02420302
030200c0
010002c3
02c30243
02430303
03030100
01400340
03400280
02800380
03800140
01800341
03410281
02810381
03810180
01c00342
03420282
02820382
038201c0
02000343
03430283
02830383
03830200
top/x400/x440_400_d_rfnoc_image_core.v
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top/x400/x440_400_d_rfnoc_image_core.vh
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//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for x440)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: x440_400_d_rfnoc_image_core.yml
//
`define CHDR_WIDTH 128
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/x400/x440_400_d_static_router.hex
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00000020
00400440
04400040
00800441
04410080
00c00442
044200c0
01000443
04430100
01400480
04800140
01800481
04810180
01c00482
048201c0
02000483
04830200
024004c0
04c00240
028004c1
04c10280
02c004c2
04c202c0
030004c3
04c30300
03400500
05000340
03800501
05010380
03c00502
050203c0
04000503
05030400
top/x400/x440_400_rfnoc_image_core.v
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top/x400/x440_400_rfnoc_image_core.vh
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//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for x440)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: x440_400_rfnoc_image_core.yml
//
`define CHDR_WIDTH 512
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/x400/x440_400_rfnoc_image_core.yml
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# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 512 # Bit width of the CHDR bus for this image
device: 'x440' # USRP type
image_core_name: 'x440_400' # Name to use for the RFNoC Image Core files
default_target: 'X440_CG_400' # Default make target
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size_bytes: 524288 # Ingress buffer size for data
ep1:
ctrl: False
data: True
buff_size_bytes: 524288
ep2:
ctrl: False
data: True
buff_size_bytes: 524288
ep3:
ctrl: False
data: True
buff_size_bytes: 524288
ep4:
ctrl: False
data: True
buff_size_bytes: 524288
ep5:
ctrl: False
data: True
buff_size_bytes: 524288
ep6:
ctrl: False
data: True
buff_size_bytes: 524288
ep7:
ctrl: False
data: True
buff_size_bytes: 524288
# A table of which crossbar routes to include
# -------------------------------------------
# Rows correspond to input ports and columns correspond to output ports.
# Entering a 1 includes and a 0 removes that route from the crossbar.
crossbar_routes:
# eth0 eth2 eth4 ep0 ep2 ep4 ep6
# eth1 eth3 dma ep1 ep3 ep5 ep7
- [ 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth0 (QSFP Port 0)
- [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] # eth1 (NC)
- [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] # eth2 (NC)
- [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] # eth3 (NC)
- [ 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth4 (QSFP Port 1)
- [ 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # dma
- [ 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep0 (radio0.0)
- [ 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep1 (radio0.1)
- [ 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep2 (radio0.2)
- [ 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep3 (radio0.3)
- [ 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep4 (radio1.0)
- [ 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep5 (radio1.1)
- [ 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep6 (radio1.2)
- [ 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep7 (radio1.3)
# A list of all NoC blocks in design
# ----------------------------------
block_chdr_width: 128 # Bit width of the CHDR bus between blocks
noc_blocks:
radio0:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 4
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl # The clock that is used for the control
# interface. This is the default clock,
# so we could skip it.
timebase_clock: _device_.radio0 # The clock that is used for the timebase.
radio1:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 4
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl
timebase_clock: _device_.radio1
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# RF A:0 TX
- { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
# RF A:0 RX
- { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
# RF A:1 TX
- { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 }
# RF A:1 RX
- { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 }
# RF A:2 TX
- { srcblk: ep2, srcport: out0, dstblk: radio0, dstport: in_2 }
# RF A:2 RX
- { srcblk: radio0, srcport: out_2, dstblk: ep2, dstport: in0 }
# RF A:3 TX
- { srcblk: ep3, srcport: out0, dstblk: radio0, dstport: in_3 }
# RF A:3 RX
- { srcblk: radio0, srcport: out_3, dstblk: ep3, dstport: in0 }
#
# RF B:0 TX
- { srcblk: ep4, srcport: out0, dstblk: radio1, dstport: in_0 }
# RF B:0 RX
- { srcblk: radio1, srcport: out_0, dstblk: ep4, dstport: in0 }
# RF B:1 TX
- { srcblk: ep5, srcport: out0, dstblk: radio1, dstport: in_1 }
# RF B:1 RX
- { srcblk: radio1, srcport: out_1, dstblk: ep5, dstport: in0 }
# RF B:2 TX
- { srcblk: ep6, srcport: out0, dstblk: radio1, dstport: in_2 }
# RF B:2 RX
- { srcblk: radio1, srcport: out_2, dstblk: ep6, dstport: in0 }
# RF B:3 TX
- { srcblk: ep7, srcport: out0, dstblk: radio1, dstport: in_3 }
# RF B:3 RX
- { srcblk: radio1, srcport: out_3, dstblk: ep7, dstport: in0 }
#
# BSP Connections
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: time0, dstblk: radio0, dstport: time }
- { srcblk: _device_, srcport: time1, dstblk: radio1, dstport: time }
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect (Always "_device"_)
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
top/x400/x440_400_static_router.hex
-17
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@@ -1,17 +0,0 @@
00000010
00400240
02400040
00800241
02410080
00c00242
024200c0
01000243
02430100
01400280
02800140
01800281
02810180
01c00282
028201c0
02000283
02830200
top/x400/x440_CG_1600_rfnoc_image_core.yml
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# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 512 # Bit width of the CHDR bus for this image
device: 'x440' # USRP type
image_core_name: 'usrp_x440_fpga_CG_1600' # Name to use for the generated output files
default_target: 'X440' # Default make target
inherit:
- 'yaml_include/x440_radio_base.yml'
- 'yaml_include/x4xx_cg_base.yml'
parameters:
RF_BW: 1600
ENABLE_DRAM: False
NUM_DRAM_BANKS: 0
NUM_DRAM_CHANS: 0
DRAM_WIDTH: 128
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size_bytes: 2097152 # Ingress buffer size for data
ep1:
ctrl: False
data: True
buff_size_bytes: 2097152
# A table of which crossbar routes to include
# -------------------------------------------
# Rows correspond to input ports and columns correspond to output ports.
# Entering a 1 includes and a 0 removes that route from the crossbar.
crossbar_routes:
# eth0 dma ep1
# eth1 ep0
- [ 1, 0, 0, 1, 1 ] # eth0 (QSFP Port 0)
- [ 0, 1, 0, 1, 1 ] # eth1 (QSFP Port 1)
- [ 0, 0, 1, 1, 1 ] # dma
- [ 1, 1, 1, 0, 0 ] # ep0 (radio0.0)
- [ 1, 1, 1, 0, 0 ] # ep1 (radio1.0)
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
radio0:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 1
NIPC: RADIO_NIPC
radio1:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 1
NIPC: RADIO_NIPC
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# RF A:0 TX
- { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
# RF A:0 RX
- { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
#
# RF B:0 TX
- { srcblk: ep1, srcport: out0, dstblk: radio1, dstport: in_0 }
# RF B:0 RX
- { srcblk: radio1, srcport: out_0, dstblk: ep1, dstport: in0 }
#
# BSP connections are inherited from YAML include files
# Clock domains are inherited from YAML include files
top/x400/x440_CG_400_rfnoc_image_core.yml
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# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 512 # Bit width of the CHDR bus for this image
device: 'x440' # USRP type
image_core_name: 'usrp_x440_fpga_CG_400' # Name to use for the generated output files
default_target: 'X440' # Default make target
inherit:
- 'yaml_include/x440_radio_base.yml'
- 'yaml_include/x4xx_cg_base.yml'
parameters:
RF_BW: 400
ENABLE_DRAM: False
NUM_DRAM_BANKS: 0
NUM_DRAM_CHANS: 0
DRAM_WIDTH: 128
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size_bytes: 524288 # Ingress buffer size for data
ep1:
ctrl: False
data: True
buff_size_bytes: 524288
ep2:
ctrl: False
data: True
buff_size_bytes: 524288
ep3:
ctrl: False
data: True
buff_size_bytes: 524288
ep4:
ctrl: False
data: True
buff_size_bytes: 524288
ep5:
ctrl: False
data: True
buff_size_bytes: 524288
ep6:
ctrl: False
data: True
buff_size_bytes: 524288
ep7:
ctrl: False
data: True
buff_size_bytes: 524288
# A table of which crossbar routes to include
# -------------------------------------------
# Rows correspond to input ports and columns correspond to output ports.
# Entering a 1 includes and a 0 removes that route from the crossbar.
crossbar_routes:
# eth0 dma ep1 ep3 ep5 ep7
# eth1 ep0 ep2 ep4 ep6
- [ 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth0 (QSFP Port 0)
- [ 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth1 (QSFP Port 1)
- [ 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # dma
- [ 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep0 (radio0.0)
- [ 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep1 (radio0.1)
- [ 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep2 (radio0.2)
- [ 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep3 (radio0.3)
- [ 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep4 (radio1.0)
- [ 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep5 (radio1.1)
- [ 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep6 (radio1.2)
- [ 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep7 (radio1.3)
# A list of all NoC blocks in design
# ----------------------------------
# Are defined in x440_radio_base.yml
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# RF A:0 TX
- { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
# RF A:0 RX
- { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
# RF A:1 TX
- { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 }
# RF A:1 RX
- { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 }
# RF A:2 TX
- { srcblk: ep2, srcport: out0, dstblk: radio0, dstport: in_2 }
# RF A:2 RX
- { srcblk: radio0, srcport: out_2, dstblk: ep2, dstport: in0 }
# RF A:3 TX
- { srcblk: ep3, srcport: out0, dstblk: radio0, dstport: in_3 }
# RF A:3 RX
- { srcblk: radio0, srcport: out_3, dstblk: ep3, dstport: in0 }
#
# RF B:0 TX
- { srcblk: ep4, srcport: out0, dstblk: radio1, dstport: in_0 }
# RF B:0 RX
- { srcblk: radio1, srcport: out_0, dstblk: ep4, dstport: in0 }
# RF B:1 TX
- { srcblk: ep5, srcport: out0, dstblk: radio1, dstport: in_1 }
# RF B:1 RX
- { srcblk: radio1, srcport: out_1, dstblk: ep5, dstport: in0 }
# RF B:2 TX
- { srcblk: ep6, srcport: out0, dstblk: radio1, dstport: in_2 }
# RF B:2 RX
- { srcblk: radio1, srcport: out_2, dstblk: ep6, dstport: in0 }
# RF B:3 TX
- { srcblk: ep7, srcport: out0, dstblk: radio1, dstport: in_3 }
# RF B:3 RX
- { srcblk: radio1, srcport: out_3, dstblk: ep7, dstport: in0 }
#
# BSP connections are inherited from YAML include files
# Clock domains are inherited from YAML include files
top/x400/x440_1600_d_rfnoc_image_core.yml → top/x400/x440_X4_1600_rfnoc_image_core.yml
+33 -36
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@@ -1,15 +1,25 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 512 # Bit width of the CHDR bus for this image
device: 'x440' # USRP type
image_core_name: 'x440_1600_d' # Name to use for the RFNoC Image Core files
default_target: 'X440_X4_1600' # Default make target
version: '1.0' # File version
chdr_width: 512 # Bit width of the CHDR bus for this image
device: 'x440' # USRP type
image_core_name: 'usrp_x440_fpga_X4_1600' # Name to use for the generated output files
default_target: 'X440' # Default make target
inherit:
- 'yaml_include/x440_radio_base.yml'
- 'yaml_include/x4xx_x4_base.yml'
parameters:
RF_BW: 1600
ENABLE_DRAM: True
NUM_DRAM_BANKS: 2
NUM_DRAM_CHANS: 2
DRAM_WIDTH: 512
# A list of all stream endpoints in design
# ----------------------------------------
@@ -36,18 +46,17 @@ stream_endpoints:
# Rows correspond to input ports and columns correspond to output ports.
# Entering a 1 includes and a 0 removes that route from the crossbar.
crossbar_routes:
# eth0 eth2 eth4 ep0 ep2
# eth1 eth3 dma ep1 ep3
- [ 1, 0, 0, 0, 0, 0, 1, 1, 1, 1 ] # eth0 (QSFP Port 0, Lane 0)
- [ 0, 1, 0, 0, 0, 0, 1, 1, 1, 1 ] # eth1 (QSFP Port 0, Lane 1)
- [ 0, 0, 1, 0, 0, 0, 1, 1, 1, 1 ] # eth2 (QSFP Port 0, Lane 2)
- [ 0, 0, 0, 1, 0, 0, 1, 1, 1, 1 ] # eth3 (QSFP Port 0, Lane 3)
- [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] # eth4 (NC)
- [ 0, 0, 0, 0, 0, 1, 1, 1, 1, 1 ] # dma
- [ 1, 1, 1, 1, 0, 1, 0, 0, 1, 1 ] # ep0 (radio0.0)
- [ 1, 1, 1, 1, 0, 1, 0, 0, 1, 1 ] # ep1 (radio1.0)
- [ 1, 1, 1, 1, 0, 1, 1, 1, 0, 0 ] # ep2 (replay0.0)
- [ 1, 1, 1, 1, 0, 1, 1, 1, 0, 0 ] # ep3 (replay0.1)
# eth0 eth2 dma ep1 ep3
# eth1 eth3 ep0 ep2
- [ 1, 0, 0, 0, 0, 1, 1, 1, 1 ] # eth0 (QSFP Port 0, Lane 0)
- [ 0, 1, 0, 0, 0, 1, 1, 1, 1 ] # eth1 (QSFP Port 0, Lane 1)
- [ 0, 0, 1, 0, 0, 1, 1, 1, 1 ] # eth2 (QSFP Port 0, Lane 2)
- [ 0, 0, 0, 1, 0, 1, 1, 1, 1 ] # eth3 (QSFP Port 0, Lane 3)
- [ 0, 0, 0, 0, 1, 1, 1, 1, 1 ] # dma
- [ 1, 1, 1, 1, 1, 0, 0, 1, 1 ] # ep0 (radio0.0)
- [ 1, 1, 1, 1, 1, 0, 0, 1, 1 ] # ep1 (radio1.0)
- [ 1, 1, 1, 1, 1, 1, 1, 0, 0 ] # ep2 (replay0.0)
- [ 1, 1, 1, 1, 1, 1, 1, 0, 0 ] # ep3 (replay0.1)
# A list of all NoC blocks in design
# ----------------------------------
@@ -57,17 +66,11 @@ noc_blocks:
parameters:
NUM_PORTS: 1
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl # The clock that is used for the control
# interface. This is the default clock,
# so we could skip it.
timebase_clock: _device_.radio0 # The clock that is used for the timebase.
radio1:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 1
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl
timebase_clock: _device_.radio1
replay0:
block_desc: 'replay.yml'
parameters:
@@ -107,14 +110,9 @@ connections:
- { srcblk: replay1, srcport: out_0, dstblk: ep3, dstport: in0 }
#
# BSP Connections
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: time0, dstblk: radio0, dstport: time }
- { srcblk: _device_, srcport: time1, dstblk: radio1, dstport: time }
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 }
- { srcblk: replay1, srcport: axi_ram, dstblk: _device_, dstport: dram1 }
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 }
- { srcblk: replay1, srcport: axi_ram, dstblk: _device_, dstport: dram1 }
# Other BSP connections are inherited from YAML include files
# A list of all clock domain connections in design
# ------------------------------------------------
@@ -124,7 +122,6 @@ connections:
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
- { srcblk: _device_, srcport: dram, dstblk: replay1, dstport: mem }
# Other clock domains are inherited from YAML include files
top/x400/x440_200_rfnoc_image_core.yml → top/x400/x440_X4_200_rfnoc_image_core.yml
+35 -39
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@@ -1,15 +1,25 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'x440' # USRP type
image_core_name: 'x440_200' # Name to use for the RFNoC Image Core files
default_target: 'X440_X4_200' # Default make target
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'x440' # USRP type
image_core_name: 'usrp_x440_fpga_X4_200' # Name to use for the generated output files
default_target: 'X440' # Default make target
inherit:
- 'yaml_include/x440_radio_base.yml'
- 'yaml_include/x4xx_x4_base.yml'
parameters:
RF_BW: 200
ENABLE_DRAM: False
NUM_DRAM_BANKS: 0
NUM_DRAM_CHANS: 0
DRAM_WIDTH: 64
# A list of all stream endpoints in design
# ----------------------------------------
@@ -52,22 +62,21 @@ stream_endpoints:
# Rows correspond to input ports and columns correspond to output ports.
# Entering a 1 includes and a 0 removes that route from the crossbar.
crossbar_routes:
# eth0 eth2 eth4 ep0 ep2 ep4 ep6
# eth1 eth3 dma ep1 ep3 ep5 ep7
- [ 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth0 (QSFP Port 0, Lane 0)
- [ 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth1 (QSFP Port 0, Lane 1)
- [ 0, 0, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth2 (QSFP Port 0, Lane 2)
- [ 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth3 (QSFP Port 0, Lane 3)
- [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] # eth4 (NC)
- [ 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # dma
- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep0 (radio0.0)
- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep1 (radio0.1)
- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep2 (radio0.2)
- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep3 (radio0.3)
- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep4 (radio1.0)
- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep5 (radio1.1)
- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep6 (radio1.2)
- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep7 (radio1.3)
# eth0 eth2 dma ep1 ep3 ep5 ep7
# eth1 eth3 ep0 ep2 ep4 ep6
- [ 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth0 (QSFP Port 0, Lane 0)
- [ 0, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth1 (QSFP Port 0, Lane 1)
- [ 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth2 (QSFP Port 0, Lane 2)
- [ 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth3 (QSFP Port 0, Lane 3)
- [ 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # dma
- [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep0 (radio0.0)
- [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep1 (radio0.1)
- [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep2 (radio0.2)
- [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep3 (radio0.3)
- [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep4 (radio1.0)
- [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep5 (radio1.1)
- [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep6 (radio1.2)
- [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep7 (radio1.3)
# A list of all NoC blocks in design
# ----------------------------------
@@ -77,17 +86,11 @@ noc_blocks:
parameters:
NUM_PORTS: 4
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl # The clock that is used for the control
# interface. This is the default clock,
# so we could skip it.
timebase_clock: _device_.radio0 # The clock that is used for the timebase.
radio1:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 4
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl
timebase_clock: _device_.radio1
duc0:
block_desc: 'duc.yml'
parameters:
@@ -163,13 +166,7 @@ connections:
- { srcblk: radio1, srcport: out_3, dstblk: ddc1, dstport: in_3 }
- { srcblk: ddc1, srcport: out_3, dstblk: ep7, dstport: in0 }
#
# BSP Connections
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: time0, dstblk: radio0, dstport: time }
- { srcblk: _device_, srcport: time1, dstblk: radio1, dstport: time }
# BSP connections are inherited from YAML include files
# A list of all clock domain connections in design
# ------------------------------------------------
@@ -179,9 +176,8 @@ connections:
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
# Other clock domains are inherited from YAML include files
top/x400/x440_400_d_rfnoc_image_core.yml → top/x400/x440_X4_400_rfnoc_image_core.yml
+45 -48
View File
@@ -1,15 +1,25 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 128 # Bit width of the CHDR bus for this image
device: 'x440' # USRP type
image_core_name: 'x440_400_d' # Name to use for the RFNoC Image Core files
default_target: 'X440_X4_400' # Default make target
version: '1.0' # File version
chdr_width: 128 # Bit width of the CHDR bus for this image
device: 'x440' # USRP type
image_core_name: 'usrp_x440_fpga_X4_400' # Name to use for the generated output files
default_target: 'X440' # Default make target
inherit:
- 'yaml_include/x440_radio_base.yml'
- 'yaml_include/x4xx_x4_base.yml'
parameters:
RF_BW: 400
ENABLE_DRAM: True
NUM_DRAM_BANKS: 2
NUM_DRAM_CHANS: 8
DRAM_WIDTH: 128
# A list of all stream endpoints in design
# ----------------------------------------
@@ -84,30 +94,29 @@ stream_endpoints:
# Rows correspond to input ports and columns correspond to output ports.
# Entering a 1 includes and a 0 removes that route from the crossbar.
crossbar_routes:
# eth0 eth2 eth4 ep0 ep2 ep4 ep6 ep8 ep10 ep12 ep14
# eth1 eth3 dma ep1 ep3 ep5 ep7 ep9 ep11 ep13 ep15
- [ 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth0 (QSFP Port 0, Lane 0)
- [ 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth1 (QSFP Port 0, Lane 1)
- [ 0, 0, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth2 (QSFP Port 0, Lane 2)
- [ 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth3 (QSFP Port 0, Lane 3)
- [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] # eth4 (NC)
- [ 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # dma
- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep0 (radio0.0)
- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep1 (radio0.1)
- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep2 (radio0.2)
- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep3 (radio0.3)
- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep4 (radio1.0)
- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep5 (radio1.1)
- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep6 (radio1.2)
- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep7 (radio1.3)
- [ 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep8 (replay0.0)
- [ 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep9 (replay0.1)
- [ 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep10 (replay0.2)
- [ 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep11 (replay0.3)
- [ 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep12 (replay0.4)
- [ 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep13 (replay0.5)
- [ 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep14 (replay0.6)
- [ 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep15 (replay0.7)
# eth0 eth2 dma ep1 ep3 ep5 ep7 ep9 ep11 ep13 ep15
# eth1 eth3 ep0 ep2 ep4 ep6 ep8 ep10 ep12 ep14
- [ 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth0 (QSFP Port 0, Lane 0)
- [ 0, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth1 (QSFP Port 0, Lane 1)
- [ 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth2 (QSFP Port 0, Lane 2)
- [ 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth3 (QSFP Port 0, Lane 3)
- [ 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # dma
- [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep0 (radio0.0)
- [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep1 (radio0.1)
- [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep2 (radio0.2)
- [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep3 (radio0.3)
- [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep4 (radio1.0)
- [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep5 (radio1.1)
- [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep6 (radio1.2)
- [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep7 (radio1.3)
- [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep8 (replay0.0)
- [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep9 (replay0.1)
- [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep10 (replay0.2)
- [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep11 (replay0.3)
- [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep12 (replay0.4)
- [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep13 (replay0.5)
- [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep14 (replay0.6)
- [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep15 (replay0.7)
# A list of all NoC blocks in design
# ----------------------------------
@@ -117,17 +126,11 @@ noc_blocks:
parameters:
NUM_PORTS: 4
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl # The clock that is used for the control
# interface. This is the default clock,
# so we could skip it.
timebase_clock: _device_.radio0 # The clock that is used for the timebase.
radio1:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 4
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl
timebase_clock: _device_.radio1
replay0:
block_desc: 'replay.yml'
parameters:
@@ -202,14 +205,9 @@ connections:
- { srcblk: replay1, srcport: out_3, dstblk: ep15, dstport: in0 }
#
# BSP Connections
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: time0, dstblk: radio0, dstport: time }
- { srcblk: _device_, srcport: time1, dstblk: radio1, dstport: time }
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 }
- { srcblk: replay1, srcport: axi_ram, dstblk: _device_, dstport: dram1 }
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 }
- { srcblk: replay1, srcport: axi_ram, dstblk: _device_, dstport: dram1 }
# Other BSP connections are inherited from YAML include files
# A list of all clock domain connections in design
# ------------------------------------------------
@@ -219,7 +217,6 @@ connections:
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
- { srcblk: _device_, srcport: dram, dstblk: replay1, dstport: mem }
# Other clock domains are inherited from YAML include files
top/x400/yaml_include/x410_radio_base.yml
+59
View File
@@ -0,0 +1,59 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'x410' # USRP type
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
radio0:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl # The clock that is used for the control
# interface. This is the default clock,
# so we could skip it.
timebase_clock: _device_.radio # The clock that is used for the timebase.
radio1:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl
timebase_clock: _device_.radio
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# BSP Connections
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect (Always "_device"_)
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
top/x400/yaml_include/x440_radio_base.yml
+57
View File
@@ -0,0 +1,57 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'x440' # USRP type
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
radio0:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 4
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl # The clock that is used for the control
# interface. This is the default clock,
# so we could skip it.
timebase_clock: _device_.radio0 # The clock that is used for the timebase.
radio1:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 4
NIPC: RADIO_NIPC
ctrl_clock: _device_.rfnoc_ctrl
timebase_clock: _device_.radio1
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# BSP Connections
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: time0, dstblk: radio0, dstport: time }
- { srcblk: _device_, srcport: time1, dstblk: radio1, dstport: time }
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect (Always "_device"_)
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
top/x400/yaml_include/x4xx_cg_base.yml
+37
View File
@@ -0,0 +1,37 @@
# A list of transport adapters to use
# -----------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
transport_adapters:
eth_qsfp0:
block_desc : 'x4xx_eth.yml'
parameters:
port_type0: 5
port_type1: 0
port_type2: 0
port_type3: 0
qsfp_num: 0
eth_qsfp1:
block_desc : 'x4xx_eth.yml'
parameters:
port_type0: 5
port_type1: 0
port_type2: 0
port_type3: 0
qsfp_num: 1
dma:
block_desc : 'chdr_dma.yml'
connections:
- {srcblk: eth_qsfp0, srcport: qsfp, dstblk: _device_, dstport: qsfp0 }
- {srcblk: eth_qsfp1, srcport: qsfp, dstblk: _device_, dstport: qsfp1 }
- {srcblk: dma, srcport: chdr_dma_s, dstblk: _device_, dstport: chdr_dma_s}
- {srcblk: _device_, srcport: chdr_dma_m, dstblk: dma, dstport: chdr_dma_m}
noc_blocks: {}
top/x400/yaml_include/x4xx_uc_base.yml
+28
View File
@@ -0,0 +1,28 @@
# A list of transport adapters to use
# -----------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
transport_adapters:
eth_qsfp1:
block_desc : 'x4xx_eth.yml'
parameters:
port_type0: 5
port_type1: 0
port_type2: 0
port_type3: 0
qsfp_num: 1
dma:
block_desc : 'chdr_dma.yml'
connections:
- {srcblk: eth_qsfp1, srcport: qsfp, dstblk: _device_, dstport: qsfp1 }
- {srcblk: dma, srcport: chdr_dma_s, dstblk: _device_, dstport: chdr_dma_s}
- {srcblk: _device_, srcport: chdr_dma_m, dstblk: dma, dstport: chdr_dma_m}
noc_blocks: {}
top/x400/yaml_include/x4xx_x4_base.yml
+28
View File
@@ -0,0 +1,28 @@
# A list of transport adapters to use
# -----------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
transport_adapters:
eth_qsfp0:
block_desc : 'x4xx_eth.yml'
parameters:
port_type0: 2
port_type1: 2
port_type2: 2
port_type3: 2
qsfp_num: 0
dma:
block_desc : 'chdr_dma.yml'
connections:
- {srcblk: eth_qsfp0, srcport: qsfp, dstblk: _device_, dstport: qsfp0 }
- {srcblk: dma, srcport: chdr_dma_s, dstblk: _device_, dstport: chdr_dma_s}
- {srcblk: _device_, srcport: chdr_dma_m, dstblk: dma, dstport: chdr_dma_m}
noc_blocks: {}
top/x400/yaml_include/x4xx_x4c_base.yml
+39
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@@ -0,0 +1,39 @@
# A list of transport adapters to use
# -----------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
transport_adapters:
eth_qsfp0:
block_desc : 'x4xx_eth.yml'
parameters:
port_type0: 2
port_type1: 2
port_type2: 2
port_type3: 2
qsfp_num: 0
eth_qsfp1:
block_desc : 'x4xx_eth.yml'
parameters:
port_type0: 5
port_type1: 0
port_type2: 0
port_type3: 0
qsfp_num: 1
dma:
block_desc : 'chdr_dma.yml'
connection: 'dma'
connections:
- {srcblk: qsfp0, srcport: qsfp, dstblk: _device_, dstport: qsfp0 }
- {srcblk: qsfp1, srcport: qsfp, dstblk: _device_, dstport: qsfp1 }
- {srcblk: dma, srcport: chdr_dma_s, dstblk: _device_, dstport: chdr_dma_s}
- {srcblk: _device_, srcport: chdr_dma_m, dstblk: dma, dstport: chdr_dma_m}
noc_blocks: {}
top/x400/yaml_include/x4xx_xg_base.yml
+37
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@@ -0,0 +1,37 @@
# A list of transport adapters to use
# -----------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
transport_adapters:
eth_qsfp0:
block_desc : 'x4xx_eth.yml'
parameters:
port_type0: 2
port_type1: 0
port_type2: 0
port_type3: 0
qsfp_num: 0
eth_qsfp1:
block_desc : 'x4xx_eth.yml'
parameters:
port_type0: 2
port_type1: 0
port_type2: 0
port_type3: 0
qsfp_num: 1
dma:
block_desc : 'chdr_dma.yml'
connections:
- {srcblk: eth_qsfp0, srcport: qsfp, dstblk: _device_, dstport: qsfp0 }
- {srcblk: eth_qsfp1, srcport: qsfp, dstblk: _device_, dstport: qsfp1 }
- {srcblk: dma, srcport: chdr_dma_s, dstblk: _device_, dstport: chdr_dma_s}
- {srcblk: _device_, srcport: chdr_dma_m, dstblk: dma, dstport: chdr_dma_m}
noc_blocks: {}