8669c68048
Most important effect of this change: rfnoc_image_builder is now required to build bitfiles, 'make' alone won't suffice any longer! This is a huge changeset to the image builder that combines multiple new features: - There no longer is a separate edge file for the static router. The static routes are generated as a Verilog parameter directly into the rfnoc_core_kernel (which is also modified). - image_builder.py is split up into several smaller files. Code is moved into yaml_utils.py, and the new files grc.py, builder_config.py - Generic module support is added. Aside from noc blocks and stream endpoints, we can now instantiate arbitrary modules (they also require a YAML description file). - To enable such modules, resets are now also tracked the same way that clock domains are. - The ImageBuilderConfig config object now more closes matches the original YAML file. The attributes 'clk_domain_con' and 'block_con' are removed. Instead, the attributes 'connections' and 'clk_domains' are sanitized and amended with extra annotations. The templates are updated to reflect this change. - IO ports can now carry parameters, e.g., to have variable wire widths based on the configuration. - Many Pylint warnings were resolved. - Add inheritance support for image core YAML files. This allows image core files to (recursively) inherit from other image core files. To do so, simply put an 'inherit' entry at the top of the file: ```yaml inherit: 'x410_radio_base.yml' ``` - The inheritance feature is used as part of the image core files. - Image core and DTS files are now generated as a build artefact into the build directory. This requires the usage of rfnoc_image_builder to build images. As a consequence, it is no longer required to check in image core Verilog files. - As another consequence, rfnoc_image_builder is required to build bitfiles! - Image flavours are no longer defined through Makefiles, but purely from the image core YAML files. - Remove all image core YAML files that do not generate a shipping image. Because of the inheritance feature and the requirement to use the image builder, it is trivial to add new YAML files. - Add support for transport adapters through the YAML files. Before, transport adapters were inferred from the make target (e.g., X410_X4_200 would have four 10GbE links based on the 'X4' substring). Now, transport adapters are defined via the image core YAML. - This feature is currently only used (or can be used) by the X4xx series. Older devices may or may not be ported to allow custom transport adapters in the future. - Add parameters to the BSP YAMLs and the devices itself. This allows setting global parameters in the image core files. For example, the X4x0 devices use this to decide if they instantiate DRAM channels. - DTS includes and constraint files can now be requested by blocks/transport adapter through their YAML files. They do no longer need to be listed in the Makefile. - Support for secure image cores. These are image cores that allow incorporating RFNoC blocks that require license keys and thus can't live in an open-source environment. This solution adds the option for secure image cores without touching the open source feature set. - Add --reuse option to allow manual editing of generated artefacts - Allow IO signatures from any module: until now IO signatures had to be defined in a single file (io_signatures). This file will persist. In addition each module can add its own IO signature as with the same format the core IO signatures placed under the top level key `io_signatures`. IO signatures are still maintained in a global dictionary. The consequence is that they can be shared among independent modules as well as they have to have a globally unique name. The image builder will warn about detected name clashes for the signatures. - As a consequence, some less commonly used IO signatures were moved to their corresponding module YAML files. Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Lars Amsel <lars.amsel@ni.com> Original-commit: a98ce2621e2a2dc25535fc700b49bfcb00b8eb59
171 lines
5.2 KiB
PHP
171 lines
5.2 KiB
PHP
#
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# Copyright 2008-2019 Ettus Research, a National Instruments Brand
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#
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##################################################
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# Project Setup
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##################################################
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# TOP_MODULE = <Input arg>
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# NAME = <Input arg>
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# PART_ID = <Input arg>
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# ARCH = <Input arg>
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##################################################
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# Include other makefiles
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##################################################
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BASE_DIR = $(abspath ..)
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IP_DIR = $(abspath ./ip)
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include $(BASE_DIR)/../tools/make/viv_design_builder.mak
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include $(IP_DIR)/Makefile.inc
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include coregen_dsp/Makefile.srcs
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include $(LIB_DIR)/ip/Makefile.inc
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include $(LIB_DIR)/hls/Makefile.inc
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include $(LIB_DIR)/control/Makefile.srcs
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include $(LIB_DIR)/fifo/Makefile.srcs
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include $(LIB_DIR)/simple_gemac/Makefile.srcs
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include $(LIB_DIR)/axi/Makefile.srcs
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include $(LIB_DIR)/timing/Makefile.srcs
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include $(LIB_DIR)/packet_proc/Makefile.srcs
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include $(LIB_DIR)/xge/Makefile.srcs
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include $(LIB_DIR)/xge_interface/Makefile.srcs
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include $(LIB_DIR)/dsp/Makefile.srcs
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include $(LIB_DIR)/axi/Makefile.srcs
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include $(LIB_DIR)/white_rabbit/wr_cores_v4_2/Makefile.srcs
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include $(LIB_DIR)/rfnoc/Makefile.srcs
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include $(BASE_DIR)/n3xx/dboards/rh/Makefile.srcs
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include $(BASE_DIR)/n3xx/dboards/mg/Makefile.srcs
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include $(BASE_DIR)/n3xx/dboards/common/Makefile.srcs
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include $(LIB_DIR)/axi4s_sv/Makefile.srcs
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include $(LIB_DIR)/rfnoc/xport_sv/Makefile.srcs
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# For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and
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# DUC, Replay, and of course the radio. Any other block needs to use the
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# RFNOC_OOT_MAKEFILE_SRCS variable (see below).
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs
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# If out-of-tree modules want to be compiled into this image, then they need to
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# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
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# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
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# source files.
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-include $(RFNOC_OOT_MAKEFILE_SRCS)
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IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
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##################################################
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# Sources
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##################################################
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TOP_SRCS = \
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n3xx_core.v \
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n3xx_mgt_channel_wrapper.v \
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n3xx_mgt_wrapper.v \
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n3xx_mgt_io_core.v \
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n3xx_clocking.v \
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n3xx_db_fe_core.v \
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WrapBufg.vhd \
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$(IMAGE_CORE)
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MB_CLOCKS_XDC = $(abspath mb_clocks.xdc)
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MB_XDC = \
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mb_timing.xdc \
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mb_pins.xdc
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ifdef BUILD_WR
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MB_XDC += $(abspath n3xx_wr.xdc)
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TOP_SRCS += \
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n3xx_wr_top.vhd \
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n3xx_serial_dac.vhd \
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n3xx_serial_dac_arb.vhd
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endif
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ifdef BUILD_10G
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MB_XDC += $(abspath n310_10ge.xdc)
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endif
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ifdef BUILD_1G
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MB_XDC += $(abspath n310_1ge.xdc)
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endif
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ifdef BUILD_AURORA
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MB_XDC += $(abspath n310_aurora.xdc)
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endif
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ifndef NO_DRAM_FIFOS
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DRAM_SRCS = $(IP_DRAM_XCI_SRCS) $(abspath n310_dram.xdc)
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else
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DRAM_SRCS =
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endif
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ifdef N300
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DB_CLOCKS_XDC =
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DB_SRCS = $(MAGNESIUM_DB_TIMING_XDC) \
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$(MAGNESIUM_DB0_XDC) \
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$(MAGNESIUM_TOP_SRCS) $(MAGNESIUM_DB_SRCS)
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endif
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ifdef N310
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DB_CLOCKS_XDC =
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DB_SRCS = $(MAGNESIUM_DB_TIMING_XDC) \
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$(MAGNESIUM_DB0_XDC) $(MAGNESIUM_DB1_XDC) \
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$(MAGNESIUM_TOP_SRCS) $(MAGNESIUM_DB_SRCS)
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endif
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ifdef N320
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DB_CLOCKS_XDC = $(RHODIUM_DB_CLOCKS_XDC)
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DB_SRCS = $(RHODIUM_DB_XDC) \
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$(RHODIUM_TOP_SRCS) $(RHODIUM_DB_SRCS)
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endif
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DB_SRCS += $(DB_COMMON_SRCS)
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# The XDC files must be read in a specific order, motherboard first and then daughterboard,
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# and the clocking XDC files must be before other XDC files.
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# Outside of that, all the other sources can be read in any order desired.
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DESIGN_SRCS = $(MB_CLOCKS_XDC) $(DB_CLOCKS_XDC) $(abspath $(MB_XDC)) $(DB_SRCS) \
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$(abspath $(TOP_SRCS)) $(AXI_SRCS) $(FIFO_SRCS) \
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$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
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$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(COREGEN_DSP_SRCS) \
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$(UDP_SRCS) $(EXTRAM_SRCS) $(WISHBONE_SRCS) \
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$(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(AURORA_PHY_SRCS) \
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$(TEN_GIGE_PHY_SRCS) $(ONE_GIGE_PHY_SRCS) \
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$(PACKET_PROC_SRCS) $(DSP_SRCS) $(DRAM_SRCS) \
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$(RADIO_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
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$(RFNOC_SRCS) $(RFNOC_OOT_SRCS) $(LIB_IP_XCI_SRCS) $(LIB_HLS_IP_SRCS) \
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$(WHITE_RABBIT_SRCS) \
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$(RFNOC_FRAMEWORK_SRCS) \
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$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
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$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) \
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$(RFNOC_BLOCK_RADIO_SRCS) \
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$(RFNOC_BLOCK_REPLAY_SRCS) \
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$(AXI4S_SV_SRCS) $(RFNOC_XPORT_SV_SRCS) \
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IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
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##################################################
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# Dependency Targets
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##################################################
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.SECONDEXPANSION:
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VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_DEF)
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# DESIGN_SRCS and VERILOG_DEFS must be defined
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bin: .prereqs
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$(call BUILD_VIVADO_DESIGN,$(abspath ./build_n3xx.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
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synth: .prereqs
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$(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
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rtl: .prereqs
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$(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
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viv_ip: .prereqs $$(DESIGN_SRCS) ip
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@echo "IP build for $(NAME) DONE . . ."
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.PHONY: bin synth rtl viv_ip
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