4d4b06dfac12b465f57852b9e8cd14e4cb8920b6
- Add different signal types - Default to real/constant - Minor cleanup Original-commit: 0624d6c6452fa47c47bb33abc1eb8ef935cfcf1f
Description
No description provided
84 MiB
Languages
Verilog
42.5%
VHDL
13%
SystemVerilog
12%
HTML
11.1%
C
9.6%
Other
11.6%