Martin Braun e44fe8625b fpga: lib: Add default wiretypes to synchronizer ...

The module was failing with missing wire types when instantiated from
another module with a default wiretype of 'none'. To fix this, this
module was also moved to no default wire type.


Original-commit: 9d1e200d5e727b34339fc4ca9b6f94b28449747a

2023-11-14 17:15:53 -06:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Add default wiretypes to synchronizer

2023-11-14 17:15:53 -06:00

sim

fpga: sim: Fix typo in clk_wait_f

2022-12-19 08:57:18 -06:00

tools

fpga: tools: Add X440_X4_200 to X440 package

2023-10-25 09:44:29 -05:00

top

fpga: x400: add default declaration for DRAM_BANKS

2023-11-14 16:23:16 -06:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

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