dbabc04cd92ab66cfd69d47a0f011dfe4a80c500
This adds support for the X440_X4_200 variant which supports up to 200 MHz bandwidth (250 Msps), has a DDC and DUC on each channel, 4 x 10 GbE interfaces, and no DRAM. Original-commit: bdaba58750ce0c2ccc58769936c3c5c4a6b2d2cf
Description
No description provided
84 MiB
Languages
Verilog
42.5%
VHDL
13%
SystemVerilog
12%
HTML
11.1%
C
9.6%
Other
11.6%