michael-west d6bcab7c8c FPGA: Add time changed pulse to timekeeper ...

The time changed signal was removed and is needed to synchronized the
frontend.  This restores the signal.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 27aad17956a063f72f192dde97cbff675b46fada

2023-05-10 14:22:42 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

FPGA: Add time changed pulse to timekeeper

2023-05-10 14:22:42 -05:00

sim

fpga: sim: Fix typo in clk_wait_f

2022-12-19 08:57:18 -06:00

tools

fpga: tools: Add X410_UC_200 image to X410 package

2023-02-24 08:07:17 -06:00

top

fpga: x4xx: Rename x410 -> x4xx for common DTS files

2023-04-24 17:27:00 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

No description provided

84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%