Ryan Marlow a90444c784 fpga: lib: Add clock_div module ...

Module description:
Clock divider. Generates an output clock that is 1/N times the
frequency of the input clock.


Original-commit: 71bdcd22f07162687771d374178ad0372783bd45

2023-04-05 15:10:14 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Add clock_div module

2023-04-05 15:10:14 -05:00

sim

fpga: sim: Fix typo in clk_wait_f

2022-12-19 08:57:18 -06:00

tools

fpga: tools: Add X410_UC_200 image to X410 package

2023-02-24 08:07:17 -06:00

top

fpga: x400: Set QSFP LEDs on startup

2023-03-24 14:02:33 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

No description provided

84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%