This implements the same change that was made for E31x. The same issue
wasn't reproduced on N3xx, however this change keeps the code
consistent and eliminates the potential for the same problem.
Original-commit: 9c4a23f0a2a2d38ace75e4ab29f6f62f64155d81
This implements the same change that was made for E31x. The same issue
wasn't reproduced on N3xx, however this change keeps the code
consistent and eliminates the potential for the same problem.
Original-commit: e94a209c5b2559348593a6732d694fd49ab59ad0
Fixing an issue in which a very slow radio_clk (due to low sample clock
rate) could cause bus transactions to be issued to the timekeeper
faster than it could service them, resulting in a timeout. This change
replaces RegPort with CtrlPort so that proper flow control can be
maintained to the timekeeper.
Original-commit: 2e910c5307702c3f3efb6dc8cb60f4f71ce11e67
It was set to E320_HG, which is not a valid target, causing build errors
unless -t E320_1G was provided to rfnoc_image_builder.
Original-commit: 9ed42affcaa88e026cb4f82807e69b546ed30c8c
Device was set to e31x, but this is not a valid device type. All e31x
devices use the e310 device type.
Original-commit: 60b76ebb31f9d1672c1b18367346b3fb522e13e9
This change prevents packets from being chopped midway if the
switchboard configuration is changed when a packet is in flight.
Original-commit: f2ec5c91a79cee4c05465349d7e0da865ad1bead
Thange allows the mux to switch cleanly between packets, if the mux
select input is changed while a packet is in flight.
Original-commit: cee09d96aee51795ba2c6578f75f25f30ea11548
The clock crossing of the ctrlport used FIFOs to transfer requests and responses
between clock domains. This commit adds a handshake based on the pulse
synchronizer to reduce the resource usage for ctrlport clock domain crossing.
Data is stored in a single register while the pulse synchronizer handles the
signaling of valid flags.
Original-commit: 2c2bb3a0b7269dcbd8b5933ce1c0c29ca17f599d
This increases the size of the ingress buffers for the N320 radio to
support 250MHz TX streaming rates.
Signed-off-by: mattprost <matt.prost@ni.com>
Original-commit: e8db6fa4301ce471bf41ef14d5d38e5727199007
This fixes some incorrectly handled clock crossings from axis_data_clk
to axis_chdr_clk, which could have manifested as timing failures (on
E320) or incorrect behavior, depending on the product and noc_shell
configuration.
Also cleans up trailing white space.
Original-commit: f48af0a0876c99016eb8cd4558a31106bfc9baa1
The max FFT size was 4096, but we don't currently have any devices that
can do that without modification. This is because, currently, the FFT
size must be the same as the packet size, and the largest packet
size supported by most devices is about 8000 bytes, or 2000
sc16 samples. Therefore, the largest FFT size supported without
modifying other code is 1024 samples.
This change frees up about 21% of the LUTs and 36% of the BRAM used by
axi_fft and makes the software block controller and the IP agree on the
maximum FFT size.
Original-commit: 4f387c8ff0571deedc86dc459e94e555b9768282
This adds additional tests to the testbench to cover register reads and
basic IFFT functionaltiy.
Original-commit: 9157e11795f3ca86dae2ee930e60a79470d1447f
This commit derives parameters for MAX10 devices if provided by the
DEVICE parameter.
MAX10 devices FIFO generator support up to 36 bit wide FIFOs using
embedded memory (M9K) in simple dual port mode, which is treated
equally to RAM in the parameters.
In combination with sorting the ctrlport signals by usage, the used
resources can be reduced on the MAX10 devices from 6 to 3 M9K blocks
for a ctrlport_clk_cross instance without time and portids.
Original-commit: 0df2f9932cc270b8f1a705ea2543df8792005878
- Detect dropped words at the dispatch level. This prevents
an overflow on CHDR from block CPU.
- Dropped packets are recorded as CPU or CHDR drop count
- Refactor to put chdr_xport_adapter.sv in different clock
domain to improve timing
- Unwrinkle tkeep/trailing transitions
Original-commit: 7f86724ec3387f75d39d683b2ac5f5152e714c74
Adding a check for bursts that cross the 4 KiB boundary to the AXI4
memory model. Crossing a 4 KiB boundary is not allowed by AXI4.
Original-commit: 24f8bb39fd2769ff93d11b21152a834500152de4
This change fixes the case where CHDR_W < ITEM_W*NIPC.
It also adds a state machine to stall the input to the pyld_fifo to
ensure that the pkt_info_fifo will not overflow. Previously in some
cases it allowed the same word to be inserted into the pyld_fifo
multiple times.
Original-commit: b862eda69cf41c7044a1805324f2fcfef5b0ba3d
This adds new image files which come with a DRAM FIFO. The addition of
an N320 image with a DRAM FIFO allows DDR3 BIST to be run on an
assembled (motherboard + daughterboard) N320.
This image is intentionally very similar to the N300_AA and N310_AA
targets which serve the same purpose of providing an image with a DRAM
FIFO for their respective devices.
Original-commit: ae2b9bf7aeea6f8f98f6dacffdfc018d87107927
- Made some things optional to reduce logic when
used with the new xport_sv:
(1) Clocking to sys_clk
(2) Preamble insertion
- New options to CUTTHROUGH faster on the TX path.
The new xport_sv already has a gate to accumulate at
its clock crossing.
Original-commit: a68e7101167a4b5bf7b60ed90d963982aae735b8
Consolidated calcuation of last_tkeep and tkeep_last. Changed error
checking to support unwrinkling tkeep/trailing changes in 100G
etherent and support for testing packet dropping on backup.
Original-commit: 473b0f5abe882ca316a7fe1a59234676940ef26b
AxiLiteBfm incorrectly included stb argument on rd() and printed actual
response instead of expected in debug message.
Original-commit: cb7e9e24578ccf4db79878a7437a6a85ad315ee2
This fixes a bug on wrstb in AxiLiteIf and adds a new AxiLiteIf_v that
can be used to stitch onto Verilog port_maps.
Original-commit: 6ef642e3ac44c52b98b124f30dc84b1683859989
This module takes an AXI-Stream without TLAST and outputs the
same AXI-Stream with TLAST based on the provided packet size
input.
Original-commit: b0b3849a18e1f2d3cb255a507b01ac5e7a9416a0
This updates the makefiles for the testbenches so they can be run using
"make modelsim" without any additional hacks. The "xsim" and "vsim"
simulation targets also still work.
Original-commit: e962cc4a5e51e2326eb656ee2a779ea26774687b
- Fixed some incorrect comments
- Fixed some missing wire declarations for internal NIC
- Fix wire declarations for GPIO (they were declared too late)
Original-commit: b18eaa75de2d1dcba2a1be0ee0b862a57e976cca
The rnfoc/xport section is refactored in System Verilog to allow the
following improvements
(1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run
at a different clock rate than the main ethernet pipe
(2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run
at a different clock rate than the main ethernet pipe
(3) ENET_W - Sets the size of the eth_tx and eth_rx pipes.
eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously
against the original xport_sv implementation, and against the new
implementation with widths of 64/128/512. A chdr_management node
info request queries the port info of the node0 in the eth_interface.
eth_ifc_synth_test.sv can be compiled with the make xsim target to test
out the size of various configurations.
Original-commit: eed4988cc266a63370a4332351d02fadedde3a3b
Wade Fife