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fpga: sim: Fix AxiLiteBfm

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AxiLiteBfm incorrectly included stb argument on rd() and printed actual
response instead of expected in debug message.


Original-commit: cb7e9e24578ccf4db79878a7437a6a85ad315ee2
This commit is contained in:
Andrew Moch
2020-07-31 13:10:00 -05:00
committed by Wade Fife
parent 6606757fa7
commit 02e4ef3318
1 changed files with 3 additions and 3 deletions
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sim/rfnoc/PkgAxiLiteBfm.sv
+3 -3
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@@ -264,7 +264,7 @@ package PkgAxiLiteBfm;
get_wr_response(xaction);
assert (xaction.resp == resp) else begin
xaction.print();
$error({"mismatch on wr response. expected:",xaction.resp.name});
$error({"mismatch on wr response. expected:",resp.name});
end
end
join_none
@@ -321,7 +321,7 @@ package PkgAxiLiteBfm;
endtask : rd_block
// Non-blocking read that checks against an expected data response
task automatic rd(addr_t addr, data_t data, strb_t strb='1,resp_t resp=OKAY);
task automatic rd(addr_t addr, data_t data, resp_t resp=OKAY);
AxiLiteTransaction_t xaction = new;
post_rd(addr,xaction);
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@@ -329,7 +329,7 @@ package PkgAxiLiteBfm;
get_rd_response(xaction);
assert (xaction.resp == resp) else begin
xaction.print();
$error({"mismatch on rd response. expected:",xaction.resp.name});
$error({"mismatch on rd response. expected:",resp.name});
end
assert (xaction.data === data) else begin
xaction.print();