Rename the BIST image cores to match the default image core names. This
eliminates the need to provide special arguments to build these images.
Original-commit: aae712c2eafe3f78ba8ed553190f7010a2d17c57
This modifies repeat_fpga_build.py such that it can take a YAML file as
input, not just a make target. It will then use the image builder to
prepare the build and generate a valid make command, which in turn is
used to build FPGA images repeatedly.
Original-commit: 09f3453f39363870f1c03ef1c917a0dedb7598df
It is, in principle, possible to use an external clock to synchronize
N3x0 devices in frequency, and then use a GPSDO for a coarse time
synchronization. This use case is deliberately not supported, as the
GPSDO PPS signal and the external clock signal are by definition not
matched, which will remove any guarantees on time/phase alignment.
Because there are certain, niche use cases where the lack of phase
alignment is acceptable, but only an external clock is available (no
shared external PPS), usage of GPS for generating a PPS signal may be
fine. This patch does not enable the usage of this combination out of
the box, but adds comments and an update to the manual to explain the
risks of this combination, and how to enable it (by patching MPM).
Original-commit: 76e004db07a3714139e64ff396a81b90c372b2bb
This utility will regenerate all the image core .v files from the
available YAML files. It won't rebuild bitfiles.
Original-commit: 4861318d3bdccd8d1baa627a8473eb34f76583b1
This removes a duplicate code section that causes build warnings. It
also references a wire that gets declared further down and the removed
and remaining code sections were incorrectly indented.
Original-commit: e8084eb4cb4ec6ff6476feb6e77ab3ea45dd969e
In the build Makefiles, this adds a function (uniq) which removes
duplicate entries from lists. We apply this to the DESIGN_SRCS passed
to the Vivado build process. This eliminates some warnings from
duplicate source files caused by redundantly referencing source files in
the Makefiles, possibly because they are listed in more than one source
file variable.
Original-commit: 1944263412d329d53b32a17e9735b79e59e319d7
In several cases, we call `python` explicitly. On many modern operating
systems (e.g., Ubuntu 22.04), this command no longer exists, and if it
does, it's often an alias to python3.
Because the python3 executable has been around for so long, simply
using that directly (instead of, e.g., autodetecting the OS preferences)
is a simple fix that immediately allows building bitfiles, e.g. for the
B2xx series, on more recent OSes.
Original-commit: 356cd172bb5ae0d043825bd1f4dffbd6646ec3d2
The module was failing with missing wire types when instantiated from
another module with a default wiretype of 'none'. To fix this, this
module was also moved to no default wire type.
Original-commit: 9d1e200d5e727b34339fc4ca9b6f94b28449747a
This updates the RFNoC image cores to separate the two DRAM banks on
X4xx by splitting them into "dram0" and "dram1". Previously, both DRAM
banks shared the same DRAM port, named "dram", which created some
confusion.
The Replay block has also been duplicated in the bitstreams that use
both banks, so we now have one Replay block per bank.
Original-commit: b5cfab8922e5b3f4ff13a8a64e8b0319876f13db
- Update X410 and X440 BSP YAML files to properly index clocks
- Update image core files to declare clock indices
- Update get_clocks() in MPM to return the correct values
This does not include changes to the x400_radio_control block registry.
This change by itself will thus not change behaviour.
Original-commit: f215af2ccde6420b685b4ca493c8bd71d28781cb
This adds support for the X440_X4_200 variant which supports up to
200 MHz bandwidth (250 Msps), has a DDC and DUC on each channel,
4 x 10 GbE interfaces, and no DRAM.
Original-commit: bdaba58750ce0c2ccc58769936c3c5c4a6b2d2cf
Adds a 266.667 MHz compute engine clock and uses it instead of the
radio clock for the DDC and DUC. Using a faster clock than the radio
allows the DDC and DUC to drain after a stall in the data flow.
Original-commit: ab93cb0929b9536b6d6cbfdc4813e6ba169053ae
Adds a 266.667 MHz compute engine clock and uses it instead of the
radio clock for the DDC and DUC. Using a faster clock than the radio
allows the DDC and DUC to drain after a stall in the data flow.
Original-commit: ff55d406a02cc934a5c238d22c836bea08ade3d1
Enable USE_AS_BUFF on packet gate to allow many packets to be buffered.
This reduces latency when several small packets are sent out close
together.
Original-commit: 32d348efe482d40c7090d8203a3c1374dfcb4a68
- Adds 6 bits each for an identifier for timebase and control clock
- Update all mako templates accordingly
Original-commit: 58c0276ff1ceaf825d7cbffbab5016ddef9a5cd9
Wade Fife