Wade Fife fc35c2a66a fpga: n3xx: Rename BIST image cores ...

Rename the BIST image cores to match the default image core names. This
eliminates the need to provide special arguments to build these images.


Original-commit: aae712c2eafe3f78ba8ed553190f7010a2d17c57

2024-03-15 00:32:53 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: rfnoc: Add EOB to source port of null_src_sink block

2024-03-12 16:05:39 -05:00

sim

fpga: sim: Fix typo in clk_wait_f

2022-12-19 08:57:18 -06:00

tools

fpga: tools: Fix -quiet in modify_bdtcl

2024-03-13 21:30:52 -05:00

top

fpga: n3xx: Rename BIST image cores

2024-03-15 00:32:53 -05:00

.gitignore

fpga: Add more spurious files to gitignore

2023-12-13 17:28:09 -06:00

build.py

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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