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fpga: rfnoc: Add EOB to source port of null_src_sink block

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Original-commit: 3a04db78e4f0bb07b63eed75416dd0164e3221df
This commit is contained in:
Francisco Salomon
2024-03-12 16:05:39 -05:00
committed by Wade Fife
parent e9700b2081
commit 2e0177484c
2 changed files with 22 additions and 5 deletions
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lib/rfnoc/blocks/rfnoc_block_null_src_sink/rfnoc_block_null_src_sink.v
+14 -4
View File
@@ -225,6 +225,7 @@ module rfnoc_block_null_src_sink #(
// NULL Source
// ---------------------------
reg reg_src_en = 1'b0;
reg reg_src_eob = 1'b0;
reg [11:0] reg_src_lpp = 12'd0;
reg [15:0] reg_src_bpp = 16'd0;
reg [9:0] reg_throttle_cyc = 10'd0;
@@ -253,6 +254,10 @@ module rfnoc_block_null_src_sink #(
if (src_pyld_tlast) begin
if (reg_throttle_cyc == 10'd0) begin
state <= ST_HDR;
if (!reg_src_en && !reg_src_eob)
reg_src_eob <= 1'b1;
else
reg_src_eob <= 1'b0;
end else begin
state <= ST_WAIT;
throttle_cntr <= reg_throttle_cyc;
@@ -263,10 +268,15 @@ module rfnoc_block_null_src_sink #(
end
end
ST_WAIT: begin
if (throttle_cntr == 10'd0)
if (throttle_cntr == 10'd0) begin
state <= ST_HDR;
else
if (!reg_src_en && !reg_src_eob)
reg_src_eob <= 1'b1;
else
reg_src_eob <= 1'b0;
end else begin
throttle_cntr <= throttle_cntr - 10'd1;
end
end
default: begin
state <= ST_HDR;
@@ -281,10 +291,10 @@ module rfnoc_block_null_src_sink #(
assign src_pyld_tvalid = (state == ST_PYLD);
assign src_ctxt_tdata = chdr_build_header(
6'd0, 1'b0, 1'b0, CHDR_PKT_TYPE_DATA, CHDR_NO_MDATA, src_pkt_cnt[15:0], reg_src_bpp, 16'd0);
6'd0, reg_src_eob, 1'b0, CHDR_PKT_TYPE_DATA, CHDR_NO_MDATA, src_pkt_cnt[15:0], reg_src_bpp, 16'd0);
assign src_ctxt_tuser = CHDR_W > 64 ? CONTEXT_FIELD_HDR_TS : CONTEXT_FIELD_HDR;
assign src_ctxt_tlast = 1'b1;
assign src_ctxt_tvalid = (state == ST_HDR && reg_src_en);
assign src_ctxt_tvalid = (state == ST_HDR && (reg_src_en || reg_src_eob));
// Register Interface
// ---------------------------
lib/rfnoc/blocks/rfnoc_block_null_src_sink/rfnoc_block_null_src_sink_tb.sv
+8 -1
View File
@@ -235,13 +235,20 @@ module rfnoc_block_null_src_sink_tb #(
for (int p = 0; p < rvalue; p++) begin
chdr_word_t exp_data[$];
chdr_word_t rx_data[$];
chdr_word_t metadata[$];
packet_info_t pkt_info;
int rx_bytes;
test.start_timeout(timeout, 5us, "Waiting for pkt to arrive");
exp_data.delete();
for (int i = p*LPP; i < (p+1)*LPP; i++)
exp_data.push_back({NIPC{{~i[ITEM_W/2-1:0], i[ITEM_W/2-1:0]}}});
blk_ctrl.recv(PORT_SRCSNK, rx_data, rx_bytes);
blk_ctrl.recv_adv(PORT_SRCSNK, rx_data, rx_bytes, metadata, pkt_info);
`ASSERT_ERROR(blk_ctrl.compare_data(exp_data, rx_data), "Data mismatch");
if (p == rvalue-1) begin
`ASSERT_ERROR(pkt_info.eob == 1, "EOB was not set on last packet from source");
end else begin
`ASSERT_ERROR(pkt_info.eob == 0, "EOB was set on middle packet from source");
end
test.end_timeout(timeout);
end
end