Wade Fife a82a2d122e fpga: Add Vivado project option to USRP FPGA builds ...

Original-commit: 2e0db35eaf69947c344f67c9f38132e33f88a141

2024-03-15 20:05:39 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: rfnoc: Add EOB to source port of null_src_sink block

2024-03-12 16:05:39 -05:00

sim

fpga: sim: Fix typo in clk_wait_f

2022-12-19 08:57:18 -06:00

tools

fpga: tools: Add option to save Vivado project

2024-03-15 20:05:39 -05:00

top

fpga: Add Vivado project option to USRP FPGA builds

2024-03-15 20:05:39 -05:00

.gitignore

fpga: Add more spurious files to gitignore

2023-12-13 17:28:09 -06:00

build.py

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

No description provided

84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%