Max Köhler c719cf1406 fpga: rfnoc: reverse FIR filter coefficients to get embedded in DSPE48 ...

Original-commit: ea164a936b924b05a5b4cb9dd50df8acc3700c1a

2024-04-26 15:19:23 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: rfnoc: reverse FIR filter coefficients to get embedded in DSPE48

2024-04-26 15:19:23 -05:00

sim

fpga: sim: Fix typo in clk_wait_f

2022-12-19 08:57:18 -06:00

tools

fpga: tools: Fix VIVADO_PROJECT variable

2024-04-02 22:48:02 -05:00

top

fpga: x400: Place SPI into IOB on X440

2024-04-09 17:12:44 -05:00

.gitignore

fpga: Add more spurious files to gitignore

2023-12-13 17:28:09 -06:00

build.py

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

No description provided

84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%