fpga: x400: zbx: Improve Lattice make flow
Original-commit: fa8559bb0f334d80e08798d415117cedf86be923
This commit is contained in:
@@ -31,7 +31,10 @@ BUILD_DIAMOND_DESIGN = \
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cp $(TOOLS_DIR)/scripts/dmd_design_build.tcl $(4)/build.tcl; \
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cd $(4); \
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echo "BUILDER: Implementating design..."; \
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pnmainc build.tcl > $(1)_log.txt ; \
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$(DIAMOND_EXE) build.tcl > $(1)_log.txt ; \
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echo "BUILDER: Parsing reports..."; \
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grep "Cumulative negative slack: 0 (0+0)" impl1/$(1)_impl1.twr ; \
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if [ $$? -ne 0 ]; then exit 1; fi; \
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echo "BUILDER: Generating bitfile..."; \
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ddtcmd -oft -svfsingle -if $(5)/$(1)_$(5).jed \
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-dev $(2) -op "FLASH Erase,Program,Verify" -revd \
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@@ -15,6 +15,12 @@ RESOLVE_PATH = $(1)
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RESOLVE_PATHS = "$(1)"
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endif
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ifeq ($(OS),Windows_NT)
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DIAMOND_EXE = "pnmainc"
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else
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DIAMOND_EXE = "diamondc"
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endif
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# -------------------------------------------------------------------
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# Project Setup
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# -------------------------------------------------------------------
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@@ -46,7 +52,7 @@ GIT_HASH_VERILOG_DEF = "GIT_HASH=32'h$(GIT_HASH)"
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@echo "BUILDER: Checking tools..."
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@echo -n "* "; bash --version | grep bash || (echo "ERROR: Bash not found in environment. Please install it"; exit 1;)
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@echo -n "* "; python3 --version || (echo "ERROR: Python not found in environment. Please install it"; exit 1;)
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@echo -n "* "; which pnmainc 2>&1 | grep diamond|| (echo "ERROR: Diamond TCL Console not found in environment."; exit 1;)
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@echo -n "* "; which $(DIAMOND_EXE) 2>&1 | grep diamond || (echo "ERROR: Diamond TCL Console not found in environment."; exit 1;)
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# -------------------------------------------------------------------
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# Intermediate build dirs
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@@ -13,11 +13,10 @@
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##
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##Output:
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## build/<device-id>/usrp_zbx_cpld_10m04.pof: Bitstream to use with JTAG programmer
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## build/<device-id>/usrp_zbx_cpld_10m04.svf: Bitstream to use with PS JTAG engine (background programming)
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## build/<device-id>/usrp_zbx_cpld_10m04.rpd: Bitstream to use via reconfig engine
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## build/<device-id>/usrp_zbx_cpld_10m04_isp_off.svf: Bitstream to use with JTAG test points (initial programming)
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## build/<device-id>/usrp_zbx_cpld_10m04_isp_off.svf: Bitstream to use with JTAG
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## build/<device-id>/usrp_zbx_cpld_xo3lf.jed: Bitstream to use with JTAG programmer
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## build/<device-id>/usrp_zbx_cpld_xo3lf.svf: Bitstream to use with PS JTAG engine (background programming)
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## build/<device-id>/usrp_zbx_cpld_xo3lf.svf: Bitstream to use with JTAG
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# Definitions
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10M04_ID = "10M04SAU324I7G"
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@@ -53,11 +52,10 @@ ifeq ($(TARGET),bin)
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cp build-$@/output_files/$(TOP)_isp_off.svf build/$(1)_10m04_isp_off.svf; \
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cp build-$@/output_files/$(TOP)_isp_on.svf build/$(1)_10m04.svf; \
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cp build-$@/output_files/$(TOP)_converted_cfm0_auto.rpd build/$(1)_10m04.rpd; \
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echo -ne "\n\n---- Make: MB CPLD ready!\n"; \
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echo -ne "\n\n---- Make: ZBX CPLD ready!\n"; \
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echo -ne " Use build/$(1).pof via JTAG programmer or\n"; \
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echo -ne " build/$(1).svf (ISP on) via PS JTAG-engine (background programming) or\n"; \
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echo -ne " build/$(1).rpd via reconfig engine or\n"; \
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echo -ne " build/$(1)_isp_off.svf via JTAG test points (initial programming)\n";
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echo -ne " build/$(1)_isp_off.svf via JTAG\n";
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else
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post_quar_build = @echo "Skipping bitfile export."
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endif
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@@ -71,8 +69,8 @@ ifeq ($(TARGET),bin)
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mkdir -p build/; \
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echo "Exporting bitstream files..."; \
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cp build-$@/$(2)/$(TOP)_$(2).svf build/$(1)_xo3lf.svf; \
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echo -ne "\n\n---- Make: MB CPLD ready!\n"; \
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echo -ne " Use build/$(1)_xo3lf.svf via PS JTAG-engine \n";
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echo -ne "\n\n---- Make: ZBX CPLD ready!\n"; \
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echo -ne " Use build/$(1)_xo3lf.svf\n";
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else
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post_dmd_build = @echo "Skipping bitfile export."
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endif
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@@ -33,6 +33,11 @@ REGS_PY_FILE=$(PROJECT_DIR)/../../../../../../../host/lib/ic_reg_maps/gen_zbx_cp
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INIT_FILES_DIR=$(PROJECT_DIR)/register_endpoints/memory_init_files/
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REGS_PY_MODULE=$(INIT_FILES_DIR)/zbx_cpld_regs_t.py
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.init_files_prereqs:
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@echo "BUILDER: Checking tools..."
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@echo -n "* "; python3 --version || (echo "ERROR: Python not found in environment. Please install it"; exit 1;)
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@echo -n "* "; python3 -c "import mako" || (echo "ERROR: Python package mako not installed. Please install it"; exit 1;)
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$(REGS_PY_MODULE): $(REGS_PY_FILE)
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@python3 $(REGS_PY_FILE) $(REGS_PY_MODULE)
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@@ -42,7 +47,7 @@ INIT_FILES := $(INIT_FILES_DIR)/rx0_path_defaults.hex
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$(INIT_FILES): $(REGS_PY_MODULE) $(INIT_FILES_DIR)/gen_defaults.py
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@python3 $(INIT_FILES_DIR)/gen_defaults.py
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cpld_defaults: .prereqs $(INIT_FILES)
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cpld_defaults: .init_files_prereqs $(INIT_FILES)
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@echo "Initialization files DONE ..."
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bin: .prereqs
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@@ -27,7 +27,7 @@
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<Source name="../../../../../../lib/control/synchronizer_impl.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../../cpld/reconfig_engine.v" type="Verilog" type_short="Verilog">
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<Source name="../../../../cpld/common/reconfig_engine.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../ctrlport_byte_deserializer.v" type="Verilog" type_short="Verilog">
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@@ -45,10 +45,10 @@
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<Source name="../../../../../../lib/wb_spi/rtl/verilog/spi_top.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../../cpld/spi_slave.v" type="Verilog" type_short="Verilog">
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<Source name="../../../../cpld/common/spi_slave.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../../cpld/spi_slave_to_ctrlport_master.v" type="Verilog" type_short="Verilog">
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<Source name="../../../../cpld/common/spi_slave_to_ctrlport_master.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../../../../lib/rfnoc/utils/ctrlport_window.v" type="Verilog" type_short="Verilog">
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