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Author SHA1 Message Date
Max Köhler 8dc5d3aeec fpga: lib: redirect old ctrlport modules to interface based ones 
Original-commit: bf294111b9f49efb6373908274bc8d31bb8cb11d
 2025-03-21 09:09:09 -05:00
Max Köhler e67d78533c fpga: bump compat number to 10.0 
Original-commit: 1cb4898519dfc2661c4537ec06faa23ed4525329
 2025-03-20 09:07:06 +01:00
Max Köhler 50f20ef4ab fpga: x4xx: replace ADC/DAC info by RFDC memory 
Original-commit: 6c6d52fd655b144aa5ee581edae7911dc734854e
 2025-03-20 09:07:06 +01:00
Max Köhler f961936a43 rfnoc: lib: introduce ctrl-port interface and BFM 
Original-commit: 886cf97ad5d494b20c6fff0a53113f6096d458c7
 2025-02-14 08:04:26 -06:00
Max Köhler c48f8bd5f1 fpga: rfnoc: lib: add AXI FIR filter for >1 SPC 
Original-commit: 90ad1fecb62b804f543def6e4c680706d76442b5
 2025-02-13 08:28:46 -06:00
Max Köhler 7446db939c fpga: x440: fix refactored rf_core_full 
Original-commit: f1fab29e4444476378faa8d435c1f76faa5a702c
 2025-02-13 07:58:10 -06:00
Max Köhler c12766fd4d fpga: x400: bump FPGA compat version to 9.0 
Original-commit: 85ef95fd85f5fdd0eb8b7792443bf3b9ce4728cf
 2025-02-12 14:38:08 +01:00
Max Köhler 4db1e1e86f fpga: lib: remove reset on non-control signals of ctrlport modules 
Original-commit: 8bdca548d1cec4c8ced3edb3c3c2ea7addc4f6e3
 2025-02-11 11:20:12 -06:00
Max Köhler be25e4da1b fpga: rfnoc: radio: move arithmetic away from timestamp for timing 
Original-commit: 7a3fc743375f065c38f9d6aa3fff43d67cc6b0e0
 2025-02-10 16:47:54 -06:00
Max Köhler b016b90dbc fpga: x400: avoid false PPS rising edge on switching sources 
Original-commit: d5876c82a02f7800141b74517d0b5461946de9fc
 2025-02-05 16:56:54 -06:00
Max Köhler 40ce83817a fpga: lib: add register stage in ipv4 chdr adapter 
Original-commit: 2b9504d84d8f8e5dd7156498b4c8b5db5a2c84da
 2025-02-05 09:14:26 -06:00
Max Köhler f4b6def040 fpga: x400: refactor 100GEth LBUS to AXI interface 
Original-commit: a218a6a503e5e4baddb939affa57b5c960ffbc84
 2025-01-31 09:08:03 -06:00
Max Köhler 067f150b75 fpga: tools: mark hash dirty with staged changes 
Original-commit: d635ee91fb34fa1fbb0c70a23337f4ea5a05cc1f
 2025-01-29 11:37:22 +01:00
Max Köhler 8d46198250 fpga: tools: Add --build-dir to repeat_fpga_build 
Original-commit: 1d1c889c15b407c2dcc5c509e3dab59aa45320e8
 2025-01-27 15:32:22 -06:00
Max Köhler 52cc1735fd fpga: lib: simplify timing in pulse stretch 
Original-commit: 2a3520b068456f1fdd291d4f8b0165e435a21757
 2025-01-23 19:18:48 -06:00
Max Köhler ccdefb0c34 fpga: x400: add CMAC placement constraints 
Original-commit: 3c8fee9c28cabb6ffdb369ca914828b1bf59884e
 2025-01-17 13:56:29 +01:00
Max Köhler 2a89218e95 fpga: x400: add rf core ctrlport 
Original-commit: a9add0a6a5baefe7dcc8fbb5a39f01dc935c7a3e
 2024-11-12 15:57:36 -06:00
Max Köhler a460c3ca2c fpga: tools: add diamond build sanity checks 
Original-commit: aa10241c7f034739da8905f862beaf0f31d286ed
 2024-09-24 10:24:29 -05:00
Max Köhler 264b33a416 fpga: x400: use parameter for RFDC info in RF core full 
Original-commit: 97d108b6f9579865f1bbd62e1c9859d290337768
 2024-09-09 10:18:59 -05:00
Max Köhler 71c7b9044d fpga: x400: add register in 100G Eth TX path for timing 
Original-commit: 7e457a190cf37b48090aebcc715a07851cbda9d2
 2024-08-30 13:23:29 -05:00
Max Köhler 82545838b2 fpga: x440: fix conditional timing constraints 
Original-commit: f407c1cc11f14fb3cef6975c62b6ba5c380aa9ce
 2024-08-27 17:22:35 -05:00
Max Köhler ea4f2ff009 fpga: x440: refactor rf_core_full to use parameters on ports 
Original-commit: 40bd20d240b2ee60ec58ad5a00a9ec9eebd1e9af
 2024-08-21 08:06:41 -05:00
Max Köhler 08f8b269fa fpga: ci: remove color coding from FPGA bitfile name 
Original-commit: eb5fe85748996675f2ec73e1f10857ba81e66c56
 2024-07-11 15:29:53 +02:00
Max Köhler 75a2526efd fpga: x400: zbx: Set Locale for ZBX Lattice build 
Original-commit: 02c1c06f708e035c9ce17d32832944bc94faf099
 2024-05-21 20:37:52 -05:00
Max Köhler 10f0bc2e79 fpga: tools: Fix VHDL and Verilog types in modify_bdtcl 
Original-commit: 041eef3472e0440730708053d47b1fb7b793c682
 2024-05-18 21:29:35 -05:00
Max Köhler c719cf1406 fpga: rfnoc: reverse FIR filter coefficients to get embedded in DSPE48 
Original-commit: ea164a936b924b05a5b4cb9dd50df8acc3700c1a
 2024-04-26 15:19:23 -05:00
Max Köhler fa95da3f7f fpga: x400: Place SPI into IOB on X440 
Placing the SPI registers into the IOB makes timing closure more
reliable.


Original-commit: 6c25d54c34f0cc4612d5c9d27e0cbd90ff248795
 2024-04-09 17:12:44 -05:00
Max Köhler a8937b3500 fpga: tools: Fix -quiet in modify_bdtcl 
Original-commit: 342221055021cbb63387362e26184d24d61746da
 2024-03-13 21:30:52 -05:00
Max Köhler e9700b2081 fpga: x4xx: add option for incremental Vivado build 
So far only the implementation after opt_run is affected by the changes.


Original-commit: 4c56b1b55ff3ae10561bd5efc83e3bb9a6a818d6
 2024-03-12 16:03:23 -05:00
Max Köhler 275373c06b fpga: tools: viv_ip_utils to update hdl_sources.tcl 
Original-commit: 1e8521f52ee9ba778d4240f1a0a197642f3cee8d
 2024-03-08 08:23:49 -06:00
Max Köhler 7be838b24c fpga: x400: zbx: Improve Lattice make flow 
Original-commit: fa8559bb0f334d80e08798d415117cedf86be923
 2024-03-05 20:07:50 -06:00
Max KöhlerHumberto JimenezJavier Valenzuela
 		7e59e9516d fpga: x400: cpld: Add support for X410 motherboard CPLD 
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>


Original-commit: 7015f5ed2d495f3908773b7c7d74864d0cc3871a
 2021-06-10 11:56:58 -05:00
Max Köhler 8eb950ac45 fpga: lib: add glitch free mux module 
Original-commit: de3b48e89f2f9711b4b97c080d5c35baba45f573
 2020-12-03 09:02:17 -06:00
Max Köhler 42d17bd090 fpga: lib: add generic to disable bitq engine tri-stating 
Original-commit: b067b2af7924aa8577a8619f97d54122e0b71daf
 2020-09-16 14:24:16 -05:00
Max Köhler ec70691e84 fpga: lib: add handshake to replace FIFO for ctrlport CDC 
The clock crossing of the ctrlport used FIFOs to transfer requests and responses
between clock domains. This commit adds a handshake based on the pulse
synchronizer to reduce the resource usage for ctrlport clock domain crossing.
Data is stored in a single register while the pulse synchronizer handles the
signaling of valid flags.


Original-commit: 2c2bb3a0b7269dcbd8b5933ce1c0c29ca17f599d
 2020-08-13 07:46:14 -05:00
Max Köhler 06afe79a42 fpga: lib: add Intel MAX10 architecture for 2clk FIFO 
This commit derives parameters for MAX10 devices if provided by the
DEVICE parameter.

MAX10 devices FIFO generator support up to 36 bit wide FIFOs using
embedded memory (M9K) in simple dual port mode, which is treated
equally to RAM in the parameters.

In combination with sorting the ctrlport signals by usage, the used
resources can be reduced on the MAX10 devices from 6 to 3 M9K blocks
for a ctrlport_clk_cross instance without time and portids.


Original-commit: 0df2f9932cc270b8f1a705ea2543df8792005878
 2020-08-06 16:17:33 -05:00
Max Köhler c33435c1b9 fpga: lib: modify ctrlport decoder to Verilog 2001 compatible syntax 
Original-commit: 4f2148e7cada5a66ce5eee92ca956cb22b31b98b
 2020-07-10 15:12:55 -05:00
Max Köhler 8875582763 fpga: lib: add extended spi core for 64bit 
The existing SPI core (simple_spi_slave.v) was limited to 32 bit. This
commit adds a second spi core with capability to transfer up to 64 bits
while keeping the same amount of resources when using generic setting
MAX_BITS = 32. Furthermore, the new module aligns mosi and miso with the
edges of sclk. The register stages were not aligned in the existing
version.


Original-commit: 366cab1fef44f1132a2acf8046ecaeac80793ccc
 2020-06-17 07:13:20 -05:00
Max Köhler 2a8ec5df90 fpga: tools: remove temporary Xilinx directories for BD recreation 
During recreation of block diagrams any RTL modules will be kept in
hidden directories within the build directory. Updates of the RTL
sources might not be taken into account. Solution is to remove Xilinx's
hidden project directories before calling vivado.


Original-commit: f17a5113e228ac1bc5312193eb8f687e127184a3
 2020-06-15 13:54:35 -05:00
Max Köhler 750317582d fpga: lib: extend wb_spi ability to limit transmission length 
Original-commit: 427a3939da459d6fb786a274ee04e28c950b71fd
 2020-06-04 14:46:19 -05:00
Max Köhler 8bc01517ae fpga: rfnoc: Add gate to dynamically enable control-port interfaces 
Original-commit: f534e9449e851a59ba8d09b0e86d189f907a8532
 2020-04-01 11:02:16 -05:00
Max Köhler 794e094218 fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1 
The latency through the combiner is static if only one master interface
is used and PRIORITY=1 is set.


Original-commit: 4e3650c0d7ac9bea3720151fbb23591f187590c7
 2020-04-01 11:02:16 -05:00
Max Köhler 6bea1f8222 fpga: lib: Modify for loop to Verilog 2001 syntax 
This changes the for loop to use the generate keyword, making it
compatible with Verilog 2001. This allows tools that only support
Verilog 2001 to use this file (e.g., Intel Quartus).


Original-commit: b92597e1c9b6f09d5e62e55a60e33c04d437a50a
 2020-03-09 13:40:17 -05:00
Max Köhler cd4cfd926c lib: add option for output register in pps generator 
The pps_generator module receives a new parameter (PIPELINE) which can
optionally add a register on the output. The default behaviour is
unchanged.


Original-commit: 3538fccfc0d9d493d767dcc445593074d3edc86d
 2020-01-28 09:35:37 -08:00