Max Köhler 82545838b2 fpga: x440: fix conditional timing constraints ...

Original-commit: f407c1cc11f14fb3cef6975c62b6ba5c380aa9ce

2024-08-27 17:22:35 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga/usrp3: Fix DC truncation bias by adding rounding to DDC chain.

2024-06-11 10:20:08 +02:00

sim

fpga: sim: Initialize test_status

2024-06-20 11:35:27 +02:00

tools

fpga: ci: remove color coding from FPGA bitfile name

2024-07-11 15:29:53 +02:00

top

fpga: x440: fix conditional timing constraints

2024-08-27 17:22:35 -05:00

.gitignore

fpga: Add more spurious files to gitignore

2023-12-13 17:28:09 -06:00

build.py

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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