Max Köhler 6bea1f8222 fpga: lib: Modify for loop to Verilog 2001 syntax ...

This changes the for loop to use the generate keyword, making it
compatible with Verilog 2001. This allows tools that only support
Verilog 2001 to use this file (e.g., Intel Quartus).


Original-commit: b92597e1c9b6f09d5e62e55a60e33c04d437a50a

2020-03-09 13:40:17 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Modify for loop to Verilog 2001 syntax

2020-03-09 13:40:17 -05:00

sim

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

tools

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

top

rfnoc: Add management filter to generic xport

2020-02-19 13:27:16 -06:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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