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Max Köhler 6bea1f8222 fpga: lib: Modify for loop to Verilog 2001 syntax 
This changes the for loop to use the generate keyword, making it
compatible with Verilog 2001. This allows tools that only support
Verilog 2001 to use this file (e.g., Intel Quartus).


Original-commit: b92597e1c9b6f09d5e62e55a60e33c04d437a50a
2020-03-09 13:40:17 -05:00
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axi
Merge FPGA repository back into UHD repository
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control
Merge FPGA repository back into UHD repository
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control_200
Merge FPGA repository back into UHD repository
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dsp
Merge FPGA repository back into UHD repository
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extramfifo
Merge FPGA repository back into UHD repository
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fifo
Merge FPGA repository back into UHD repository
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fifo_200
Merge FPGA repository back into UHD repository
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gpif2
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hls
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io_cap_gen
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io_port2
Merge FPGA repository back into UHD repository
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ip
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packet_proc
Merge FPGA repository back into UHD repository
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packet_proc_200
Merge FPGA repository back into UHD repository
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radio_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
rfnoc
fpga: lib: Modify for loop to Verilog 2001 syntax
2020-03-09 13:40:17 -05:00
sim
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
simple_gemac
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
timing
fixup! lib: add option for output register in pps generator
2020-02-05 09:26:57 -06:00
vita_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
vivado_ipi
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
wb_spi
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
white_rabbit/wr_cores_v4_2
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
wishbone
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xge
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
xge_interface
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
zpu
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
zynq_fifo
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00