Max Köhler 794e094218 fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1 ...

The latency through the combiner is static if only one master interface
is used and PRIORITY=1 is set.


Original-commit: 4e3650c0d7ac9bea3720151fbb23591f187590c7

2020-04-01 11:02:16 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1

2020-04-01 11:02:16 -05:00

sim

sim: Rename class typedefs

2020-03-09 13:43:05 -05:00

tools

fpga: tools: Add default Vivado install location

2020-04-01 08:45:41 -05:00

top

rfnoc: Add management filter to generic xport

2020-02-19 13:27:16 -06:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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