b210-k7-fpga

35 Commits 1 Branch 0 Tags

3 Commits

Author	SHA1	Message	Date
Max Köhler	794e094218	fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1 The latency through the combiner is static if only one master interface is used and PRIORITY=1 is set. Original-commit: 4e3650c0d7ac9bea3720151fbb23591f187590c7	2020-04-01 11:02:16 -05:00
Max Köhler	6bea1f8222	fpga: lib: Modify for loop to Verilog 2001 syntax This changes the for loop to use the generate keyword, making it compatible with Verilog 2001. This allows tools that only support Verilog 2001 to use this file (e.g., Intel Quartus). Original-commit: b92597e1c9b6f09d5e62e55a60e33c04d437a50a	2020-03-09 13:40:17 -05:00
Max Köhler	cd4cfd926c	lib: add option for output register in pps generator The pps_generator module receives a new parameter (PIPELINE) which can optionally add a register on the output. The default behaviour is unchanged. Original-commit: 3538fccfc0d9d493d767dcc445593074d3edc86d	2020-01-28 09:35:37 -08:00

Author

SHA1

Message

Date

Max Köhler

794e094218

fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1

The latency through the combiner is static if only one master interface
is used and PRIORITY=1 is set.


Original-commit: 4e3650c0d7ac9bea3720151fbb23591f187590c7

2020-04-01 11:02:16 -05:00

Max Köhler

6bea1f8222

fpga: lib: Modify for loop to Verilog 2001 syntax

This changes the for loop to use the generate keyword, making it
compatible with Verilog 2001. This allows tools that only support
Verilog 2001 to use this file (e.g., Intel Quartus).


Original-commit: b92597e1c9b6f09d5e62e55a60e33c04d437a50a

2020-03-09 13:40:17 -05:00

Max Köhler

cd4cfd926c

lib: add option for output register in pps generator

The pps_generator module receives a new parameter (PIPELINE) which can
optionally add a register on the output. The default behaviour is
unchanged.


Original-commit: 3538fccfc0d9d493d767dcc445593074d3edc86d

2020-01-28 09:35:37 -08:00