Max Köhler 10f0bc2e79 fpga: tools: Fix VHDL and Verilog types in modify_bdtcl ...

Original-commit: 041eef3472e0440730708053d47b1fb7b793c682

2024-05-18 21:29:35 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: rfnoc: reverse FIR filter coefficients to get embedded in DSPE48

2024-04-26 15:19:23 -05:00

sim

fpga: sim: Fix cast in PkgRandom

2024-05-16 09:30:05 -05:00

tools

fpga: tools: Fix VHDL and Verilog types in modify_bdtcl

2024-05-18 21:29:35 -05:00

top

fpga: x400: Place SPI into IOB on X440

2024-04-09 17:12:44 -05:00

.gitignore

fpga: Add more spurious files to gitignore

2023-12-13 17:28:09 -06:00

build.py

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%