Max Köhler 10f0bc2e79 fpga: tools: Fix VHDL and Verilog types in modify_bdtcl ...

Original-commit: 041eef3472e0440730708053d47b1fb7b793c682

2024-05-18 21:29:35 -05:00

..

make

fpga: tools: Fix VIVADO_PROJECT variable

2024-04-02 22:48:02 -05:00

scripts

fpga: tools: Fix VHDL and Verilog types in modify_bdtcl

2024-05-18 21:29:35 -05:00

utils

fpga: utils: Use default image core name

2024-03-15 00:32:53 -05:00