This modifies repeat_fpga_build.py such that it can take a YAML file as
input, not just a make target. It will then use the image builder to
prepare the build and generate a valid make command, which in turn is
used to build FPGA images repeatedly.
Original-commit: 09f3453f39363870f1c03ef1c917a0dedb7598df
This utility will regenerate all the image core .v files from the
available YAML files. It won't rebuild bitfiles.
Original-commit: 4861318d3bdccd8d1baa627a8473eb34f76583b1
In the build Makefiles, this adds a function (uniq) which removes
duplicate entries from lists. We apply this to the DESIGN_SRCS passed
to the Vivado build process. This eliminates some warnings from
duplicate source files caused by redundantly referencing source files in
the Makefiles, possibly because they are listed in more than one source
file variable.
Original-commit: 1944263412d329d53b32a17e9735b79e59e319d7
In several cases, we call `python` explicitly. On many modern operating
systems (e.g., Ubuntu 22.04), this command no longer exists, and if it
does, it's often an alias to python3.
Because the python3 executable has been around for so long, simply
using that directly (instead of, e.g., autodetecting the OS preferences)
is a simple fix that immediately allows building bitfiles, e.g. for the
B2xx series, on more recent OSes.
Original-commit: 356cd172bb5ae0d043825bd1f4dffbd6646ec3d2
FPGA:
- Split up MB registers that control daughterboard specific settings so
that daughterboards 0 and 1 could have different setings, in
preparation for future devices that require different settings.
This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
block/tile mapping of the individual channels, and information about
resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
them to their own headers, so it's trivial to add device-specific
sections of code instead for other devices in the future.
- This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
was unused and possibly broken.
- Move daughterboard-specific code into its own code location
(dboards/zbx)
- Move X410-specific register documentation to its own location
(doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
timekeeper)
MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
Adds a BUILD_BASE_DIR makefile variable that allows you to specify the
base directory for FPGA build outputs. This allows you to put the
output from each run of make into a unique directory, or to run
multiple instances of make in parallel with each build's output being
put in a different directory. For example:
make X310_XG BUILD_BASE_DIR=/path/to/builds
Original-commit: bc6db8409ba756bbad0d0c158ffb00c614b58fd9
This fixes recognition of $error and $fatal statements in the output of
XSim when running run_testbenches.py. XSim apparently prints a "shift
in" character (0x15) as part of its error statements, so the regular
expression was not matching.
Original-commit: ee36d7fabcf73f773edae00fbb1604a600db992d
The main changes included are:
- Variant-dependent pin-out instantiation.
- Update clocking scheme in top level file
to include XO3 PLL
- Add ability to shift outgoing data for
the GPIO communication interface with
the X410 FPGA.
- Include project files required to build
the XO3 variant of the ZBX CPLD.
- Add build flow for Lattice Diamond designs.
- Add ability to build XO3 variant of ZBX CPLD.
Original-commit: 2c7813acb21383f302353a1b6cf57f0946fa0b6b
USRP N230 is no longer supported starting with UHD 4, and thus, we can
remove it from the image manifest. This will no longer download N230
images when calling uhd_images_downloader from UHD 4.
Original-commit: f1f6d8eac52bfecd840ace95c2d357641ae3b09c
This change causes HLS IP to be exported with a version of 1.0.0
instead of a date code. Due to a bug in Vivado, date codes after
0x7FFFFFFF (anything in 2022 or beyond) cause an error. Setting
an explicit revision avoids this issue.
See Xilinx AR 76960 for details.
Original-commit: 51384afc2c5d4db9e2e45d97382edce8c8039b10
This commit refactors the X410's CPLDs build process to make it similar to other
FPGA targets within the repo. The new process relies on basic Quartus build
utilities.
Additionally, this commit adds support for an alternative MAX10 CPLD for the
motherboard CPLD implementation. Both previous (10M04) and new variant
(10M08) are supported concurrently. The images package mapping is updated to
reflect these changes.
Original-commit: e1ce4565dbc7336ee806adce7c087bda4fcc77ae
Updates the language in setupenv.sh --help to better reflect that there
are many locations where Vivado is searched.
Original-commit: e64d3e28316f642c1203722b6f5f2af710a7e281
This adds a Verilog definition named `UHD_FPGA_DIR that corresponds to
the location of the UHD "fpga" directory. This allows you to include
files in your out-of-tree modules relative to the FPGA directory. For
example, you could include the library header file rfnoc_chdr_utils.vh
using the following:
`include `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`"
Some simulators may not support `" outside of the context of a `define,
in which case you can do the following:
`define RFNOC_CHDR_UTILS_PATH \
`"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`"
`include `RFNOC_CHDR_UTILS_PATH
Original-commit: 66267f515802ff3f965fd44e1f0d3097ada7484f
This sets the ARCH and PART_ID environment variables so that the
selected part family is used for simulations by default. This can be
overridden by changing them in the Makefile for the testbench if a
testbench requires a specific part family. Prior to this change, the
default was always ARCH=kintex7, PART_ID=xc7k410t/ffg900/-2, which
required support for that part to be installed.
Original-commit: c176046dff4941bcec27b0b72e5a68264c4808e5
The script was previously only Python 2 compatible.
Python 2 support is now removed, so we don't maintain backwards
compatibility with Python 2.
This also fixes all linter warnings.
Original-commit: 6046e1a812ba2065d6ae13b4c4afdce8abc99d4f
PkgComplex adds functions for doing complex arithmetic in SystemVerilog
simulation.
PkgMath provides mathematical operations and constants that aren't
built into SystemVerilog, such as a constant for pi and the function
round().
PkgRandom adds randomization functions beyond what standard Verilog
supports but that don't require any special licenses or simulators.
Original-commit: da4202e6f74796603072aa14544581604e81df02
This change allows assertion errors/failures in ModelSim to be
detected and causes ModelSim to return a non-zero value when such
an assertion error occurs. This allows the return value of ModelSim
to be used to determine whether or not the testbench passed.
Original-commit: 574146ec8909da367c3441189c2877a287892f7e
VHDL depends on the compile order. This commit changes the order so
that SIM_SRCS are compiled last with ModelSim to avoid issues with
dependencies.
Original-commit: b85b796cbc1f897a69ded1f3ecfba8ec92684c11
This updates the existing PART_NAME generation used in simulation
makefiles to work with newer part families by calling
viv_gen_part_id.py to generate the part name needed by Vivado.
Original-commit: 648c70ae758ab1d15c7ec6cbe57672e8c27640cd
This is a list of testbenches that don't work with ModelSim and should
be excluded when running run_testbenches.py.
Original-commit: 6190eca14ec13db7456a059cbd69c93550aa45c7
Max Köhler