Give curr_word a complete combinational assignment and use blocking assignments in chdr_16sc_to_12sc.
This removes the two 64-bit latch banks and the resulting bogus inferred-clock timing endpoints while preserving all legal FSM-state behavior.
Replace broad GPIF/radio false paths with 10 ns datapath-only maximum delays between the 100 MHz GPIF clock and the generated SISO/MIMO radio clocks.
Preserve physical control of asynchronous CDC paths without overriding the more-specific XPM FIFO CDC constraints.
Create generated clock copies on the shared radio BUFGMUX output and mark the full-rate SISO and divide-by-two MIMO modes logically exclusive.
This prevents static timing from attempting impossible cross-mode hold fixes while retaining valid timing relationships outside the shared clock tree.
Synchronize legacy and XPM reset indications into the FIFO read clock domain instead of feeding cross-domain reset logic into asynchronous PRE/CLR paths.
This removes the FIFO-induced CDC-10 findings while preserving legacy reset behavior.
Use the real axi_fifo_2clk hierarchy with XPM-based asynchronous FIFO implementations instead of synthesizing axi_fifo_2clk_sim.
Map the deep stream FIFOs into dedicated block RAM while preserving the legacy FWFT FIFO interface.
A missing "else" after 6ea4e48 was causing two configurations to occur
at the same time for some values of SIZE.
This commit also sets the "space" and "occupied" outputs to 0 when in
pass-through mode.
Original-commit: 19b5c85b514e1c37238308e405108c69ecbddb7e
This brings back the package PkgChdrUtils after it was removed in
d9f8c08. Its contents were moved because most of the contents were
synthesizable, but many existing testbenches might still reference the
old package name. This new version of PkgChdrUtils simply imports then
exports the things it used to include. New testbenches are encouraged
to reference the new files instead of PkgChdrUtils.
Original-commit: 7992198889c172db04dd324bac42819c51d6ee79
Add -assert option to Vivado synthesis to allow VHDL assert statements
to be checked during synthesis.
Original-commit: 13d004fa9001823e807c4a2b72e92b20efb6f94a
This change sets StdArithNoWarnings and NumericStdNoWarnings by
default for ModelSim simulations. Without this, an excessive number of
warnings can be generated by Xilinx IP during simulation.
Original-commit: f094aa7ae0f864764276c5c67c51b21547327fb0
This changes the -onfinish setting from "stop" to "final" for Questa
and ModelSim. The "final" setting is required so that SystemVerilog
final blocks run. This also has the same effect as "stop" in that it
won't ask you in the GUI if you want to exit the simulator when
$finish() is called.
Original-commit: 7ab4e9a4e2c0408ca595ad168199a54bf416c894
This commit addresses several issues that can occur with different
simulators. It changes the following:
- Update documentation
- Ignore testbenches in build-ip folders
- Tolerate extra lines in the testbench results regular expression
- Match numbers using \d instead of + to avoid ValueError exceptions
- Only fetch the start_time if it exists
- Allow any simulator make target (don't limit it to specific choices)
Original-commit: 81ccd8cb5154e85636cddd86c466daffb4ab4ebe
This adds the NIPC parameter, which configures support for processing
multiple items or samples per clock cycle. With this enabled, the FFT
block can process at rates higher than 250 MSPS, such as 500 MSPS and
beyond.
Original-commit: fc76aa940e121fe1f85a3513f6d90df4667338cf
On the CPU to Ethernet path (c2e) in some configurations the trailing
bytes length was not being properly set in TUSER. This can lead to
extra bytes being added onto packets. Most of the time this is fine,
since the extra bytes would be ignored by the underlying protocols.
But when the packet was near the MTU size, it could lead to an
oversized packet that would get dropped by the network or host
computer.
Original-commit: 00d9a228f58b384798f0a1346fbab8f40b017a9c
This wrapper was using TUSER for the number of trailing bytes, but it
wasn't properly enabled, which could cause it to be ignored in some
cases.
Original-commit: e7ebe601163d01d157bc3de9c2652952932e4a1c
This was set to 1 in UHD 4.7, but it must be 2 for all channels to
have sufficient bandwidth.
Original-commit: b012c18fd653714e84b1d4a86e27ff90fe13ae04
Fixed an issue where the DDC could experience an arithmetic overflow
when receiving a full-scale signal with non-zero DDS frequency.
Original-commit: 5030d0106b6d2230a1c28e72f765098c7916cf1b
This reverts commit e572bab3ee5aa40f57bdc6e11d6381cad1d1401a.
The problem with skipping the "unnecessary" bash wrappers is that Ubuntu
systems use 'dash' as a default shell, which does not support our build
infrastructure. While we do recommend not using dash for building FPGA
builds in our documentation, it's not obvious that dash is the problem
when calling rfnoc_image_builder.
Original-commit: 888850d6417c93f561e0555c693e3f11e9f40856
Radio command FIFO will back pressure commands until there is room
for new elements.
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Original-commit: 474a17020e649e9ae4a39ef7cbce810d0ec67983
miegl
Wade Fife