Give curr_word a complete combinational assignment and use blocking assignments in chdr_16sc_to_12sc.
This removes the two 64-bit latch banks and the resulting bogus inferred-clock timing endpoints while preserving all legal FSM-state behavior.
Replace broad GPIF/radio false paths with 10 ns datapath-only maximum delays between the 100 MHz GPIF clock and the generated SISO/MIMO radio clocks.
Preserve physical control of asynchronous CDC paths without overriding the more-specific XPM FIFO CDC constraints.
Create generated clock copies on the shared radio BUFGMUX output and mark the full-rate SISO and divide-by-two MIMO modes logically exclusive.
This prevents static timing from attempting impossible cross-mode hold fixes while retaining valid timing relationships outside the shared clock tree.
Synchronize legacy and XPM reset indications into the FIFO read clock domain instead of feeding cross-domain reset logic into asynchronous PRE/CLR paths.
This removes the FIFO-induced CDC-10 findings while preserving legacy reset behavior.
Use the real axi_fifo_2clk hierarchy with XPM-based asynchronous FIFO implementations instead of synthesizing axi_fifo_2clk_sim.
Map the deep stream FIFOs into dedicated block RAM while preserving the legacy FWFT FIFO interface.
miegl